US 10,992,301 B1Granted

Circuit and method for generating temperature-stable clocks using ordinary oscillators

AssigneeMicrosemi Semiconductor ULC

InventorsKrste Mitric, Kamran Rahbar

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Abstract

A circuit for generating temperature-stable clocks including first and second crystal oscillators, an input for a reference clock source, a clock output, a first phase acquisition circuit coupled to the first and second crystal oscillators, a second phase acquisition circuit coupled to the input for the reference clock source and to the second crystal oscillator, a first DPLL coupled to the first phase acquisition circuit, a crystal oscillator variation estimator coupled to the first DPLL, a second DPLL coupled to the second phase acquisition circuit and including a phase-frequency detector having a input coupled to the second phase acquisition circuit, a loop filter, a frequency subtractor having an input coupled to the loop filter and an input coupled to the crystal oscillator variation estimator, and a DCO coupled to the frequency subtractor and driving an input of the phase-frequency detector.

Claims18

Dependent claims

A circuit for generating a temperature-stable clock comprising:

a first crystal oscillator;
a second crystal oscillator;
an input for a reference clock source;
a clock output;
a first phase acquisition circuit coupled to an output of the first crystal oscillator and to an output of the second crystal oscillator;
a second phase acquisition circuit coupled to the input for the reference clock source and to an output of the second crystal oscillator;
a first digital phase locked loop (DPLL) coupled to an output of the first phase acquisition circuit;
a crystal oscillator variation estimator coupled to an output of the first DPLL;
and
a second DPLL coupled to an output of the second phase acquisition circuit, the second DPLL including:
a phase-frequency detector having a first input coupled to the output of the second phase acquisition circuit;
a loop filter;
a frequency subtractor having a first input coupled to an output of the loop filter and a second input coupled to an output of the crystal oscillator variation estimator;
and
a digital controlled oscillator (DCO) coupled to an output of the frequency subtractor, an output of the DCO coupled to a second input of the phase-frequency detector and coupled to the clock output.

12 more elements

A method for generating temperature-stable clocks comprising:

providing first and second crystal oscillators;
providing a memory that stores temperature characterization polynomial coefficients generated during initial production and characterization of the first and second crystal oscillators obtained by curve fitting frequency variations of the second crystal oscillator over temperature versus frequency differences between the first and second crystal oscillators over temperature;
measuring the phase difference between the first crystal oscillator and the second crystal oscillator;
phase locking a high-bandwidth first digital phase locked loop (DPLL) to the measured phase difference between the first crystal oscillator and the second crystal oscillator;
estimating frequency variations of the second crystal oscillator responsive to frequency information based on the measured phase difference, and responsive to the stored temperature characterization polynomial coefficients;
providing a reference clock signal from a reference clock source;
measuring the phase difference between the reference clock signal and the second crystal oscillator;
phase locking a second DPLL to the phase difference between the reference clock signal and the second crystal oscillator;
adjusting the frequency of the second DPLL by the estimated frequency variation of the second crystal oscillator;
and
providing an output from the second DPLL.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/816,113Filed 11 Mar 2020 · us provisional application
Priority: 9 Jan 2020
Granted: 27 Apr 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H03L 1/027
By indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature: by using frequency…
H03L 7/087
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using at least two…
H03L 7/07
Using a reference signal applied to a frequency- or phase-locked loop: using several loops, e.g. for redundant clock signal generation
H03L 7/0994
The oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider: comprising an accumulator

Family

Application62/959,074Us provisional application · filed 9 Jan 2020
US 10,992,301 B1This patent

From the US filing history. Foreign family members aren’t listed.

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