PLL system with master and slave devices

A method of controlling one or more slave devices each including a respective first digitally controlled oscillator (DCO) controlled by an output of a second DCO in a master phase locked loop device, comprising:

• generating timing pulses in the master phase locked loop device by a master synchronization timer;
• synchronizing at least one replica synchronization timer with master timing pulses received from said master phase locked loop device;
• reading phase and frequency information from said output of said second DCO;
• transmitting said read phase and frequency information to said one or more slave devices over a peripheral interface;
• and
• updating the first DCO in the respective slave device of the one or more slave devices with said transmitted phase and frequency information based on timing pulses generated by said at least one replica synchronization timer.

A system comprising:

• a master phase locked loop device working in association with one or more slave devices including at least one slave digitally controlled oscillator (sDCO), the master PLL device comprising:
• at least one digital PLL (DPLL) channel including a master digitally controlled oscillator (mDCO) having a higher resolution than said at least one sDCO;
• a master synchronization timer for generating master timing pulses to permit reading phase and frequency information from said mDCO;
• a peripheral interface for sending said read frequency and phase information to said one or more slave devices;
• and
• a master synchronization interface for sending said master timing pulses to synchronize a replica synchronization timer in said at least one sDCO that generates slave timing pulses for use in updating said phase and frequency information received at said one or more slave devices;
• wherein said one or more slave devices, comprise:
• a slave digitally controlled oscillator controlled by phase and frequency information obtained from the master PLL device;
• and
• a replica synchronization timer for generating replica timing pulses to permit reading of phase and frequency information received from the master PLL device, said replica synchronization timer being responsive to timing pulses received from the master PLL device to synchronize said replica synchronization timer with said synchronization timer in the master device.