Circuits and methods for transferring two differentially encoded client clock domains over a third carrier clock domain between integrated circuits

A method for transferring, via a carrier clock signal in a carrier clock domain, a first client clock signal in a first client clock domain and a second client clock signal in a second client clock domain between a first and a second integrated circuit, comprising:

• providing a stable reference clock source to the first integrated circuit;
• generating, in the first integrated circuit, the carrier clock signal from the stable reference clock source and phase locking the generated carrier clock signal to the stable reference clock source;
• providing a first client clock signal in the first client clock domain to the first integrated circuit;
• phase locking a first client clock signal DPLL to the first client clock signal;
• providing a second client clock signal in the second client clock domain to the first integrated circuit;
• phase locking a second client clock signal DPLL to the second client clock signal;
• latching a present phase of the first client clock signal and encoding a phase change of the first client clock signal since a last latched phase of the first client clock signal as first phase word information in first bit positions;
• latching a present phase of the second client clock signal and encoding a phase change of the second client clock signal since a last latched phase of the second client clock signal as second phase word information in second bit positions different from the first bit positions;
• and
• modulating the carrier clock signal to generate and send first and second phase word information and non-phase word information over a single wire in designated sub-frame slots from the first integrated circuit to the second integrated circuit.