Clock synthesizer with integral non-linear interpolation (inl) distortion compensation

A clock synthesizer with nonlinear digital-to-time conversion compensation driven by system clock pulses, comprising:

• a first path comprising a first digital controlled oscillator (DCO) responsive to an input frequency value Freq to generate output clock pulses, a first digital-to-time converter (DTC) for linearly interpolating between system clock pulses to correct the phase of the output clock pulses, a first compensation module for applying compensation values to the first DTC to correct for INL distortion, and an adjustable delay module for introducing a series of nominal analog delays I*dt, (I=0, 1, . . . N−1), where N*dt=1/fsys, into an output of the first DCT;
• a second path comprising a second digital controlled oscillator (DCO) responsive to said input frequency value Freq to generate output clock pulses, a second digital-to-time converter (DTC) for linearly interpolating to a series of M interpolation points k between system clock pulses to correct the phase of the output clock pulses, and a delay memory for applying nominal initial delays I*D, (I=0,1 . . . N−1), where N*D=Freq, to the second DCO, and a second compensation module for applying a compensation values to the second DTC to correct for INL distortion;
• a controller programmed to:
• (i) introduce a selected nominal analog delay I*dt with an actual delay of I*dt+δ, where δ is a small offset from the nominal delay, at the output of the first path and a nominal digital delay I*D with an actual delay of I*D+Δ, where Δ is a small offset from the nominal delay, at the input of the second path that offsets the actual analog delay in the first path;
• (ii) adjust contents x(k) of the second compensation module to align the output clock pulses from the first and second paths for different values of k;
• (iii) iteratively repeat steps (i) and (ii) for all N values of I;
• and
• (iv) average the contents x(k) of the second compensation module to derive the compensation values to be applied to a selected one of said DTCs to correct for INL distortion.

A clock synthesizer with nonlinear digital-to-time conversion compensation driven by system clock pulses, comprising:

• a first path comprising a first digital controlled oscillator (DCO) responsive to an input frequency value Freq to generate output clock pulses, a first digital-to-time converter (DTC) for linearly interpolating between system clock pulses to correct the phase of the output clock pulses, a first compensation module for applying compensation values to the first DTC to correct for INL distortion, and an adjustable delay module for introducing a series of nominal analog delays I*dt, (I=0, 1, . . . N−1), where N*dt=1/fsys, into an output of the first DCT;
• a second path comprising a second digital controlled oscillator (DCO) responsive to said input frequency value Freq to generate output clock pulses, a second digital-to-time converter (DTC) for linearly interpolating to a series of M interpolation points k between system clock pulses to correct the phase of the output clock pulses, and a delay memory for applying nominal initial delays I*D, (I=0,1 . . . N−1), where N*D=Freq, to the second DCO, and a second compensation module for applying a compensation values to the second DTC to correct for INL distortion;
• a controller programmed to introduce a selected nominal analog delay I*dt with an actual delay of I*dt+δ, where δ is a small offset from the nominal delay, at the output of the first path and a nominal digital delay I*D with an actual delay of I*D+Δ, where Δ is a small offset from the nominal delay, at the input of the second path that offsets the actual analog delay in the first path.