Axis Semiconductor, Inc.
Methuen, MA, US· latest recorded location
Axis Semiconductor, Inc. is named on 7 US grants and 6 published applications in this corpus. Its most frequent classification is G06F (Computing and data processing).
- Granted patents
- 7
- Published applications
- 6
- Inventors
- 10
- Granted in 2026 so far
- 0
- Most recent grant
- 22 Aug 2023
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2008 | 0 | 1 |
| 2009 | 0 | 0 |
| 2010 | 0 | 0 |
| 2011 | 1 | 0 |
| 2012 | 2 | 0 |
| 2013 | 0 | 2 |
| 2014 | 1 | 1 |
| 2015 | 0 | 0 |
| 2016 | 0 | 0 |
| 2017 | 0 | 0 |
| 2018 | 0 | 0 |
| 2019 | 0 | 0 |
| 2020 | 1 | 0 |
| 2021 | 0 | 0 |
| 2022 | 1 | 2 |
| 2023 | 1 | 0 |
By publication year.
Technology areas
Share of 13 documents
Recent patents
- Computing device with circuit switched memory access22 Aug 2023US 11,734,211 B2
- Energy efficient microprocessor with index selected hardware architecture27 Sep 2022US 11,455,272 B2
- Method of synchronizing host and coprocessor operations via FIFO communication18 Feb 2020US 10,565,036 B1
- Dynamically reconfigurable hybrid circuit-switched and packet-switched network architecture19 Aug 2014US 8,811,387 B2
- Instruction set design, control and communication in programmable microprocessor cores and the like15 May 2012US 8,181,003 B2
- Energy efficient microprocessor with index selected hardware architecture16 Jun 2022US 2022/0188264 A1
- Computing device with circuit switched memory access2 Jun 2022US 2022/0171731 A1
- Efficient high performance scalable pipelined searching method using variable stride multibit tries10 Apr 2014US 2014/0101150 A1
- Hierarchical multi-core processor and method of programming for efficient data processing30 May 2013US 2013/0138919 A1
- Dynamically reconfigurable hybrid circuit-switched and packet-switched network architecture21 Feb 2013US 2013/0044634 A1
Most cited
By later US patents
- Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing11US 8,099,583 B22012
- Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions5US 8,078,833 B22011
- Instruction set design, control and communication in programmable microprocessor cores and the like2US 8,181,003 B22012