Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing

A flexible data pipeline structure for accommodating software computational instructions for varying program applications, comprising:

• a programmable embedded processor having a plurality of pipeline stages, the pipeline stages including mathematical execution units and memory units;
• a switch matrix, each of the pipeline stages having a direct connection to the switch matrix, the switch matrix being able to form direct interconnections between the pipeline stages, the direct interconnections between the pipeline stages being variable in response to varying program application instructions, the processor including program memory for storing application instructions from a compiler;
• and
• at least one instruction fetch and decode unit connected to the program memory;
• the switch matrix selectively interconnecting pluralities of the mathematical execution units and memory units so as to directly interconnect the pipeline stages in any desired number and in any desired order, the switch matrix being controllable by at least one switch control unit having local storage of at least one switch control vector, the switch matrix being also controllable by commands received from the at least one instruction fetch and decode unit;
• the switch matrix providing full access switching with any allowable connections between any two pipeline stages, and with the switch matrix connecting to a DMA;
• and
• the interconnections between the pipeline stages being reconfigurable and operating modes of at least some of the pipeline stages being changeable under control of each individual instruction as it is executed.

A method of processing computer software computational instructions fed to a processor, the method comprising:

• compiling and analyzing inputted user software applications to determine the specific computational tasks that need to be performed for each software application;
• generating a set of instruction sequences for each software application, including a set of configuration sequences of the processor functional components and of the connections among them required for that specific software application;
• and
• under control of the individual instructions as they are executed, forming direct interconnections between functional components of the processor through switching of an interconnecting switch, each of the pipeline stages having a direct connection to the interconnecting switch, the interconnecting switch being able to form direct interconnections between the pipeline stages, thereby forming a logical data pipeline having any desired number and order of functional components, interconnections between the functional components being reconfigurable and operating modes of at least some of the functional components being changeable under control of each individual instruction as it is executed.