US 2013/0138919 A1Published application

Hierarchical multi-core processor and method of programming for efficient data processing

AssigneeAxis Semiconductor, Inc.

InventorsXiaolin Wang, Qian Wu, Ben Marshall, John Eppling, Jie Sun

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Abstract

A multi-core processor includes a tree-like structure having a plurality of computing cores arranged in hierarchical levels, the cores all having the same logical architecture. Each core can include computing, interconnecting, and/or storage elements. The functionality of an individual element can be supplied by an entire core in a lower level. A method for programming the processor includes hierarchically decomposing an application into interconnected sub-functions, mapping the sub-functions onto groups of cores at appropriate levels of the processor, and interconnecting the mapped sub-functions so as to hierarchically compose the complete application. Sub-functions can be sequential, concurrent, and/or pipelined. Interconnections can be static or dynamically switchable under program control. Interconnect elements can also be used to implement flow control as needed in pipelined operations to maintain data coherency. The decomposing and mapping process can be iterated on sub-functions so as to optimize load balancing, software performance, and hardware efficiency.

Claims21

Dependent claims

A multi-core processor, comprising:

a plurality of processing cores, referred to herein as computing planes,
the computing planes being arranged in a hierarchy of levels including a highest level and a lowest level, each of the levels including at least one computing plane,
each of the computing planes including a control plane and an associated datapath,
each of the control planes including a sequencing instruction memory that is able to store configuration and control information applicable to its associated data path, the configuration information including instructions that control manipulation and routing of data by its associated datapath,
each of the control planes being able to receive status information from its associated data path, and being able to provide configuration and control information to its associated data path,
each of the datapaths including at least one data input, at least one data output, and at least one element, the element being one of a compute element that is able to manipulate data, an interconnect element that is able to route data, and a storage element that is able to store data, and
for at least one of the elements that is in a level above the lowest level, the functionality of the element being provided by a computing plane in a level below the level of the element.

4 more elements

Dependencies are inferred from the claim text.