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AssigneeAxis Semiconductor, Inc.
InventorsXiaolin Wang, Qian Wu, Benjamin Marshall, Fugui Wang, Gregory Pitarys, Ke Ning
Estimating the term…
Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.
A method of clock cycle synchronized flexible programmable execution of a data processing program, the method comprising:
A clock-cycle synchronized flexible programmable data processor comprising:
Dependencies are inferred from the claim text.