Computing device with circuit switched memory access

Abstract

A computing device includes a transport switch comprising read and write switches that provide switched circuit interconnections between input and output ports for simultaneous data communication between a plurality of memory clients and a plurality of memory banks, such as between cores of a multi-core processor simultaneously accessing L1, L2, and L3 memory banks. Embodiments implement switching designs that are derived from existing switched network architectures. Other embodiments implement a novel circuit switch design based on 8×8 building blocks. The transport switch can be non-blocking, and can be self-routing. An additional switching layer can be included to provide port rearrangement for rearrangeable non-blocking switches. A transport compiler can be used to determine port-pair configurations of the switch. A disclosed method selects optimal switch architectures for specific applications. Embodiments support simultaneous, multicast transfers of data retrieved from a memory bank to a plurality of memory clients.

Dependencies are inferred from the claim text.