Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions

A programmable embedded processor with internal pipeline stages, at least some of the pipeline stages being mathematical execution units and at least some of the pipeline stages being memory units;

• and
• an interconnecting switch matrix, each of the pipeline stages having a direct connection to the interconnecting switch matrix, the interconnecting switch matrix being able to form direct interconnections between the pipeline stages, the direct interconnections between the pipeline stages being variable in response to varying application instruction sequences as fast as every clock cycle so as to interconnect the pipeline stages in any desired number and in any desired order,
• wherein each of the execution units includes a plurality of logic circuits, the logic circuits being interconnectable into different hierarchical architecture structures so as to perform operations at different precisions of multi-bit arithmetic and logic operations, and
• wherein each of the execution units includes a program RAM into which control settings can be loaded for configuration of the logic circuits into different hierarchical architecture structures in the execution unit.

A flexible data pipelining method accommodating software algorithms for varying application programs, the method comprising:

• programming an embedded data processor with internal pipeline stages, at least some of the pipeline stages being mathematical execution units and at least some of the pipeline stages being memory units, each of the execution units including a plurality of logic circuits, each of the execution units including a program RAM into which control settings can be loaded for interconnecting of the logic circuits into different hierarchical architecture structures in the execution unit, each of the pipeline stages having a direct connection to an interconnecting switch matrix;
• forming direct interconnections between the pipeline stages, the direct interconnections between the pipeline stages being formed by the matrix switch and being variable in response to varying application instruction sequences as fast as every clock cycle so as to interconnect the pipeline stages in any desired number and in any desired order;
• loading control settings into the program RAM of the execution units so as to interconnect the logic circuits into different hierarchical architecture structures which cause the execution units to perform at different precisions of multi-bit arithmetic and logic operations;
• and
• configuring the memory units to perform memory read and memory write in desired memory addressing modes, and in a multi-level hierarchical fashion.