H03L 2207/14
Preventing false-lock or pseudo-lock of the pll
Official title: Preventing false-lock or pseudo-lock of the PLL
H03L2207/14 (Preventing false-lock or pseudo-lock of the pll) appears on 105 US grants and 57 published applications in this corpus.
Search patents in H03L- Granted patents
- 105
- Published applications
- 57
- Assignees
- 78
- Inventors
- 161
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 1 | 0 |
| 1978 | 0 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 1 | 0 |
| 1982 | 1 | 0 |
| 1983 | 2 | 0 |
| 1984 | 0 | 0 |
| 1985 | 1 | 0 |
| 1986 | 1 | 0 |
| 1987 | 1 | 0 |
| 1988 | 2 | 0 |
| 1989 | 1 | 0 |
| 1990 | 1 | 0 |
| 1991 | 2 | 0 |
| 1992 | 1 | 0 |
| 1993 | 2 | 0 |
| 1994 | 1 | 0 |
| 1995 | 3 | 0 |
| 1996 | 1 | 0 |
| 1997 | 3 | 0 |
| 1998 | 0 | 0 |
| 1999 | 2 | 0 |
| 2000 | 4 | 0 |
| 2001 | 9 | 0 |
| 2002 | 7 | 9 |
| 2003 | 3 | 3 |
| 2004 | 6 | 8 |
| 2005 | 5 | 5 |
| 2006 | 6 | 4 |
| 2007 | 3 | 1 |
| 2008 | 5 | 1 |
| 2009 | 1 | 1 |
| 2010 | 0 | 1 |
| 2011 | 2 | 5 |
| 2012 | 4 | 2 |
| 2013 | 4 | 2 |
| 2014 | 2 | 4 |
| 2015 | 2 | 1 |
| 2016 | 1 | 1 |
| 2017 | 1 | 0 |
| 2018 | 1 | 1 |
| 2019 | 0 | 0 |
| 2020 | 0 | 1 |
| 2021 | 4 | 2 |
| 2022 | 0 | 1 |
| 2023 | 4 | 0 |
| 2024 | 0 | 2 |
| 2025 | 1 | 1 |
| 2026 | 2 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Circuit apparatus and oscillator8 Sep 2026US 12,732,135 B2Seiko Epson Corporation
- Single and dual-edge triggered phase error detection24 Mar 2026US 12,587,199 B2Microchip Technology Incorporated
- Determining a locked status of a clock tracking circuit9 Dec 2025US 12,494,789 B2Microchip Technology Incorporated
- Initialization circuit of delay locked loop7 Mar 2023US 11,601,130 B2NXP B. V.
- Obtaining lock in a phase-locked loop (PLL) upon being out of phase-lock21 Feb 2023US 11,588,489 B1Shaoxing Yuanfang Semiconductor Co., Ltd.
- Single and dual-edge triggered phase error detection23 Jul 2026US 2026/0213754 A1Microchip Technology Incorporated
- Circuit apparatus and oscillator3 Jul 2025US 2025/0219579 A1Seiko Epson Corporation
- Single and dual edge triggered phase error detection14 Mar 2024US 2024/0088902 A1Microchip Technology Incorporated
- Determining a locked status of a clock tracking circuit14 Mar 2024US 2024/0088904 A1Microchip Technology Incorporated
- Initialization circuit of delay locked loop29 Dec 2022US 2022/0416796 A1NXP B. V.
Most cited
By later US patents
- Synchronous clock generator including a false lock detector132US 5,940,609 AMicorn Technology, Inc. · 1999
- Multiple channel adaptive data recovery system90US 6,463,109 B1Vitesse Semiconductor Corporation · 2002
- Signal delay apparatus employing a phase locked loop81US 5,179,303 ANorthern Telecom Limited · 1993
- Wide frequency-range delay-locked loop circuit80US 6,326,826 B1Silicon Image, Inc. · 2001
- Means for control limits for delay locked loop73US 5,663,665 ACypress Semiconductor Corporation · 1997