US 11,588,489 B1Granted

Obtaining lock in a phase-locked loop (PLL) upon being out of phase-lock

AssigneeShaoxing Yuanfang Semiconductor Co., Ltd.

InventorsRakesh Kumar Gupta, Nitesh Naidu, Raja Prabhu J, Srinath Sridharan, Ankit Seedher, Shivam Agrawal

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Abstract

A phase-locked loop (PLL) provided according to an aspect of the present disclosure includes a phase detector, a low-pass filter, an oscillator, an output block and a phase locking block. The oscillator generates an intermediate clock and the output block generates each of successive cycles of a feedback clock on counting a pre-determined number of cycles of the intermediate clock. The phase locking block, upon detecting the PLL being out of phase-lock, controls the operation of the output block to obtain phase-lock in the PLL within two cycles of the input clock from the time of detection of the PLL being out of phase-lock.

Claims20

Dependent claims

A phase-locked loop (PLL) comprising:

a phase detector coupled to receive a first input clock on an input path and a feedback clock on a feedback path, said phase detector to generate an error signal representing a phase difference between said first input clock and said feedback clock;
a low-pass filter to generate a filtered error signal by filtering said error signal;
an oscillator coupled to generate an intermediate clock from said filtered error signal, wherein a frequency of said intermediate clock is determined by a magnitude of said filtered error signal;
an output block to generate each of successive cycles of said feedback clock on counting of a pre-determined number of cycles of said intermediate clock;
and
a phase locking block to detect said PLL being out of phase-lock, and controlling said output block to lock phase of said PLL within two cycles of said first input clock from said detecting.

3 more elements

A system comprising:

a line card coupled to receive a data packet, said line card to re-time said data packet with reference to a selected clock, and to transmit a re-timed packet;
a first timing card to generate a first clock;
and
wherein said line card comprises a phase-locked loop (PLL) coupled to receive said first clock, said PLL to provide an output clock based on said first clock as said selected clock, wherein said PLL comprises:
a phase detector coupled to receive said first clock and a feedback clock, said phase detector to generate an error signal representing a phase difference between said first clock and said feedback clock;
a low-pass filter to generate a filtered error signal by filtering said error signal;
an oscillator coupled to generate an intermediate clock from said filtered error signal, wherein a frequency of said intermediate clock is determined by a magnitude of said filtered error signal;
an output block comprising:
a divider coupled to receive said intermediate clock and to generate each of successive cycles of a divided clock on counting of a pre-determined number of cycles of said intermediate clock;
and
a gating block to forward said divided clock as said feedback clock if said PLL is in phase-lock, and to not forward said divided clock as said feedback clock for a portion of a duration in which said PLL is out of phase-lock;
and
a phase locking block comprising:
a phase threshold-crossing detector to detect, based on said error signal, said PLL going out of phase-lock from a steady-state;
and
a reset-generator block to, following detection of said PLL going out of phase-lock, restart said divider to start counting said pre-determined number of cycles synchronous with said first clock to cause said divider to thereafter count said pre-determined number of cycles before generating each next cycle of said successive cycles,
wherein said feedback clock is said output clock of said PLL.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/662,660Filed 10 May 2022
Priority: IN 2021410455016 Oct 2021
Granted: 21 Feb 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H03L 7/091
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: the phase or…
H03L 7/0814
And where no voltage or current controlled oscillator is used: the phase shifting device being digitally controlled
H03L 7/099
Details of the phase-locked loop: concerning mainly the controlled oscillator of the loop
H03L 7/0992
The oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider: comprising a counter or a…