Single and dual-edge triggered phase error detection

An apparatus, comprising:

• a phase detector to set a status signal that indicates a status of phase difference between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock;
• a sampling logic circuit to generate samples of the status signal by sampling the status signal of the phase detector at a set sampling rate;
• a decimator to decimate the status signal at a decimation rate to generate decimated samples;
• an interpolator to interpolate the status signal at an interpolation rate to generate interpolated samples;
• a multiplexer to select between the decimated samples and the interpolated samples at least partially based on a sampling rate selection;
• and
• a digital discriminator to:
• receive the selected samples;
• and
• generate a locked status signal indicative of a locked status of the clock tracking circuit at least partially based on the selected samples.

An apparatus, comprising:

• a sampling clock divider to:
• generate a divided reference clock and a divided feedback clock by dividing a reference clock and a feedback clock, respectively using a sampling rate;
• a phase detector to receive the divided reference clock and the divided feedback clock and set a status signal;
• and
• a digital discriminator to:
• receive samples of the status signal at the sampling rate;
• and
• generate a locked status signal indicative of a locked status of a clock tracking circuit at least partially based on the samples of the status signal.