Wide frequency-range delay-locked loop circuit
AssigneeSilicon Image, Inc.
InventorsKyeongho Lee, Deog-Kyoon Jeong
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Abstract
A delay-locked loop (DLL), including frequency detection logic and a phase detector, is described having an operating range as wide as a conventional charge pump phase locked loop. The frequency detector logic counts the number of rising edges of the multi-phase clocks generated from a reference clock during one period of the reference clock. A loop filter is used to adjust the frequency of each multi-phase clock until frequency lock is obtained by comparing the number of rising edges. After frequency lock, phase detection logic is used to finely tune out the remaining phase error.
Claims15
A delay-locked loop for generating a set of multiphase clocks whose delays are locked to an input reference signal, comprising:
- a plurality of delay elements adapted to incrementally delaying the input reference clock to generate a set of multi-phase clocks;
- a frequency detector logic adapted to counting the number of rising edges of said set of multi-phase clocks in one period of said input reference clock;
- and
- a loop filter adapted to generating a control signal to adjust the delay amount of each delay element when the number of rising edges is different from a predetermined number.
A delay-locked loop for generating a set of multiphase clocks whose delays are locked to an input reference signal, comprising:
- means for delaying the input reference clock by incremental delays to generate a set of multi-phase clocks;
- means for counting the number of rising edges of said set of multi-phase clocks in one period of said input reference clock;
- and
- means for adjusting the incremental delays when the number of rising edges of said multiphase clocks is different from a predetermined number.
A method of generating a set of multiphase clocks whose delays are locked to an input reference signal, comprising:
- generating a set of multi-phase clocks in response to a reference clock;
- counting the number of rising edges of said set of multi-phase clocks in one period of said input reference clock;
- and
- adjusting the frequency of each multi-phase clock when the number of rising edges is different from a predetermined number.
Dependencies are inferred from the claim text.