Initialization circuit of delay locked loop

A delay locked loop (DLL), comprising:

• an initialization circuit comprising:
• a sense circuit configured to receive a first enable signal, a reference clock signal, and a set of delayed clock signals that is generated based on the reference clock signal, and output a second enable signal;
• and
• a control circuit coupled with the sense circuit, and configured to receive the first and second enable signals and output a first control signal;
• and
• a loop filter that is coupled with the control circuit, and configured to receive the first control signal and a second control signal and output a reference voltage to control a first delay value associated with the DLL, wherein during an initialization of the DLL, the reference voltage is outputted based on the first control signal such that the first delay value equals a predetermined delay value for a predetermined time duration, and after a lapse of the predetermined time duration, the first delay value increases until a difference between a time period of the reference clock signal and the first delay value equals a threshold value, and wherein after the initialization of the DLL, the reference voltage is outputted based on the second control signal such that the first delay value further increases until the first delay value equals the time period of the reference clock signal.

A system-on-chip, comprising:

• a clock circuit configured to output a reference clock signal;
• and
• a delay locked loop (DLL), comprising:
• an initialization circuit comprising:
• a sense circuit coupled with the clock circuit, and configured to receive a first enable signal, the reference clock signal, and a set of delayed clock signals that is generated based on the reference clock signal, and output a second enable signal;
• and
• a control circuit coupled with the sense circuit, and configured to receive the first and second enable signals and output a first control signal;
• and
• a loop filter that is coupled with the control circuit, and configured to receive the first control signal and a second control signal and output a reference voltage to control a first delay value associated with the DLL, wherein during an initialization of the DLL, the reference voltage is outputted based on the first control signal such that the first delay value equals a predetermined delay value for a predetermined time duration, and after a lapse of the predetermined time duration, the first delay value increases until a difference between a time period of the reference clock signal and the first delay value equals a threshold value, and wherein after the initialization of the DLL, the reference voltage is outputted based on the second control signal such that the first delay value further increases until the first delay value equals the time period of the reference clock signal.