H03D 13/003
In which both oscillations are converted by logic means into pulses which
Official title: {in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means}
H03D13/003 (In which both oscillations are converted by logic means into pulses which) appears on 460 US grants and 256 published applications in this corpus.
Search patents in H03D- Granted patents
- 460
- Published applications
- 256
- Assignees
- 226
- Inventors
- 697
- Latest grant
- 16 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 3 | 0 |
| 1978 | 1 | 0 |
| 1979 | 1 | 0 |
| 1980 | 4 | 0 |
| 1981 | 4 | 0 |
| 1982 | 4 | 0 |
| 1983 | 3 | 0 |
| 1984 | 2 | 0 |
| 1985 | 1 | 0 |
| 1986 | 4 | 0 |
| 1987 | 0 | 0 |
| 1988 | 3 | 0 |
| 1989 | 7 | 0 |
| 1990 | 5 | 0 |
| 1991 | 3 | 0 |
| 1992 | 7 | 0 |
| 1993 | 4 | 0 |
| 1994 | 9 | 0 |
| 1995 | 6 | 0 |
| 1996 | 14 | 0 |
| 1997 | 15 | 0 |
| 1998 | 11 | 0 |
| 1999 | 12 | 0 |
| 2000 | 26 | 0 |
| 2001 | 20 | 5 |
| 2002 | 20 | 23 |
| 2003 | 25 | 31 |
| 2004 | 30 | 29 |
| 2005 | 26 | 32 |
| 2006 | 34 | 37 |
| 2007 | 28 | 25 |
| 2008 | 29 | 27 |
| 2009 | 20 | 9 |
| 2010 | 26 | 5 |
| 2011 | 14 | 6 |
| 2012 | 6 | 3 |
| 2013 | 6 | 3 |
| 2014 | 5 | 3 |
| 2015 | 2 | 0 |
| 2016 | 5 | 6 |
| 2017 | 5 | 0 |
| 2018 | 0 | 2 |
| 2019 | 1 | 1 |
| 2020 | 3 | 2 |
| 2021 | 1 | 0 |
| 2022 | 0 | 2 |
| 2023 | 3 | 2 |
| 2024 | 0 | 0 |
| 2025 | 1 | 2 |
| 2026 | 1 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Frequency correction loop with deadzone and hysteresis16 Jun 2026US 12,658,927 B2Renesas Electronics America Inc.
- Systems and methods for phase locked loop realignment with skew cancellation22 Jul 2025US 12,368,444 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Adaptive control of bias settings in a digital microphone7 Nov 2023US 11,811,904 B2InvenSense, Inc.
- Systems and methods for phase locked loop realignment with skew cancellation19 Sep 2023US 11,764,791 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Systems and methods for phase locked loop realignment with skew cancellation3 Jan 2023US 11,545,983 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Frequency correction loop with deadzone and hysteresis19 Feb 2026US 2026/0051893 A1Renesas Electronics America Inc.
- Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation16 Oct 2025US 2025/0323649 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Phase frequency detector and its method of operation11 Sep 2025US 2025/0286541 A1Indian Institute of Technology Ropar
- Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation30 Nov 2023US 2023/0387918 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation13 Apr 2023US 2023/0111482 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Digital variable in-lock range phase comparator119US 5,619,148 AAdvanced Micro Devices, Inc. · 1997
- Digital phase/frequency detector, and clock generator and data recovery PLL containing the same118US 6,683,930 B1Cypress Semiconductor Corporation · 2004
- Method for shaping a pulse width and circuit therefor117US 5,892,380 AMotorola, Inc. · 1999
- Clock and data recovery scheme for multi-channel data communications receivers114US 6,307,906 B1Applied Micro Circuits Corporation · 2001
- Continuously tuneable frequency steerable frequency synthesizer having frequency lock for precision synthesis107US 5,266,907 ATimeback FLL · 1993