Digital variable in-lock range phase comparator
AssigneeAdvanced Micro Devices, Inc.
InventorBin Guo
Life of this patent
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Abstract
A novel method and apparatus providing an all digital phase comparator of two binary signals which employs a type of cross correlation of two binary signals and provides a 2bit binary word uniquely representative of phase alignment. The method can be carried out using a pair of flip-flop (FF) circuits, each FF having a docking input and a data input, and where each FF has a delay in series with its data input.
Claims17
A new method for using a flip flop circuit including a first pair of D type flip flops including first DFF and second DFF DFF as a digital phase comparator for indicating the phase angle relationship between a first binary signal PHO and a second binary signal PHK wherein said first and second binary signals exhibit a duty cycle distortion TDCD and wherein said first DFF has a clock input, a D input and an RTOK output and said second DFF has a clock input, a D input and an RTKO output comprising,
- connecting said PHO signal to said clock input of said first DFF and delaying said PHO signal by a first delay time TWSM, where TWSM is greater than said duty cycle distortion TDCD, and feeding said delayed PHO signal to said D input of said second DFF;
- connecting said PHK signal to the clock input of said second DFF and delaying said PHK signal by a second delay time where said second delay time is greater than said duty cycle distortion and feeding said PHK signal to the D input of said first DFF;
- simultaneously sampling and latching the levels of said RTOK output and RTKO output;
- analyzing the logic levels of said latched RTOK output and RTKO output in combinatorial logic and providing a plurality of unique phase range indications including a smallest phase range indication, which range indications are indicative of whether PHK needs to be delayed more or less or whether the phase angle is within the smallest indicator phase range of said first pair of flip flops with respect to a phase angle between PHO and PHK of 360 degrees.
A new method for using a flip flop circuit including a first pair of D type flip flops including first DFF and second DFF DFF as a digital phase comparator for indicating the phase angle relationship between a first binary signal PHO and a second binary signal PHK wherein said first and second binary signals exhibit a duty cycle distortion TDCD and wherein said first DFF has a clock input, a D input and an RTOK output and said second DFF has a clock input, a D input and an RTKO output comprising,
- connecting said PHO signal to said clock input of said first DFF and delaying said PHO signal by a first delay time TWSM, where TWSM is greater than said duty cycle distortion TDCD, and feeding said delayed PHO signal to said D input of said second DFF;
- connecting said PHK signal to the clock input of said second DFF and delaying said PHK signal by a second delay time where said second delay time is greater than said duty cycle distortion and feeding said PHK signal to the D input of said first DFF;
- simultaneously sampling and latching the levels of said RTOK output and RTKO output;
- analyzing the logic levels of said latched RTOK output and RTKO output in combinatorial logic and providing a plurality of unique phase range indications including a smallest phase range indication, which range indications are indicative of whether PHK needs to be delayed more or less or whether the phase angle is within the smallest indicator phase range of said first pair of flip flops with respect to a phase angle between PHO and PHK of 360 degrees;
- a second pair of D type flip flop connected to said PHO and PHK, said second pair of D type flip flops including a third and fourth D flip flop DFF, said third and fourth DFF being interconnected to said PHO and to said PHK and to one another in exactly the same manner as said first and second DFF, wherein said third DFF has an output STOK and said fourth DFF has an output STKO;
- feeding said PHO signal to the clock input of said third DFF and delaying said PHO signal by a third time delay and feeding said delayed PHO signal to the D input of said fourth DFF;
- feeding said PHK signal to the clock input of said fourth DFF and delaying said PHK signal by a fourth delay time and feeding said PHK signal to the D input of said third DFF, said third and fourth time delays being of equal delay time but where said third and fourth time delays do not equal the delay of said first delay time or said second time delay;
- simultaneously sampling and latching the levels of said STOK and STKO;
- analyzing the logic levels of said STOK and STKO in combinatorial logic and providing a plurality of unique phase range indications including a smallest phase range indication, which range indications are indicative of whether PHK needs to be delayed more or less or whether the phase angle between PHO and PHK is within the smallest phase range indication of said second pair of flip flops.
A digital phase comparator circuit for comparing the time delay between a first and second binary signal comprising:
- a first flip flop unit FF1 unit, said FF1 unit having a first and second input terminals and one output terminal, one of said FF1 unit input terminals being a terminal to receive said first binary signal, said FF1 unit including a first and second delay element;
- a second flip flop unit FF2 unit, said FF2 unit having a first and second input terminals and one output terminal, one of said FF2 unit input terminals being a terminal to receive said second binary signal, said FF2 unit including a first and second delay element;
- said FF1 unit and said FF2 unit including the same flip flop type;
- and
- said first input terminal of said FF1 unit being connected to said second input terminal of said FF2 unit and said second input terminal of FF1 unit being connected to said first input terminal of FF2 unit, said FF1 unit and said FF2 unit both including,
- (i) a first and second D flip flop DFF, each said DFF having a clock input and a D input, said clock input of said first DFF being connected to said first input terminal of said FF1 and said clock input of said second DFF being connected to said second input terminal of said first FF1;
- and
- (ii) each said delay element having an input and an output;
- said output of said first delay element being connected to said D input of said first DFF and said output of said second delay element being connected to said D input of said second DFF, where said first delay element input of said FF1 unit is connected to said second input terminal of said FF1 unit and wherein said first delay element input of said FF2 unit is connected to said second input terminal of said FF2 unit, and
- where said second delay element input of said FF1 unit is connected to said first input terminal of said FF1 unit and wherein said second delay element of said FF2 unit is connected to said first input terminal of said FF2 unit;
- and
- latch means, said latch means being a third FF3 and fourth FF4D type flip flop, each said FF3 and FF4 having a D input, a clock input, and an output, said D input of said FF3 and FF4 being connected to said output terminal of said first D flip flop of FF1 unit and to said output terminal of said second D flip flop of FF1 unit respectively, said FF3 and FF4 being connected to detect and hold the state of the output at said output terminal of said first and second D flip flops respectively of said FF1 unit, said clock inputs of said FF3 and FF4 being connected together and to a terminal for receiving a clocking pulse.
A method of comparing the phase of a first and second binary signal wherein at least one of said first and second binary signals exhibit duty cycle distortion TDCD comprising:
- delaying each said first and second binary signals by an amount TWSM to provide a first delayed signal and a second delayed signal respectively, said amount TWSM being greater than said TDCD;
- sampling said first binary signal by said second delayed signal and storing the sampled level in a first latch;
- sampling said second binary signal by said first delayed signal and storing the sampled level in a second latch;
- combinatorially analyzing said stored values in said latches, and providing a unique logic level indication of the phase relationship of said first and second binary signals.
Dependencies are inferred from the claim text.