Digital phase/frequency detector, and clock generator and data recovery PLL containing the same
AssigneeCypress Semiconductor Corporation
InventorKamal Dalmia
Life of this patent
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Abstract
An apparatus comprising a first circuit, a second circuit and a logic circuit. The first circuit may be configured to generate a first output signal having a first data rate in response to an input signal having a second data rate and clock signal having the second data rate. The second circuit may be configured to generate a second output signal in response to the input signal and the clock signal. The logic circuit may be configured to generate a clock signal in response to the first output signal and the second output signal.
Claims21
An apparatus comprising:
- a phase detector circuit configured to generate a first output signal having a first data rate in response to (i) a data input signal having a second data rate and (ii) a clock signal having said second data rate;
- a frequency detector circuit configured to generate a second output signal having a third data rate in response to (i) said data input signal and (ii) said clock signal;
- and
- a logic circuit configured to generate said clock signal in response to (i) said first output signal and (ii) said second output signal.
An apparatus comprising:
- means for using a phase detector for generating a first output signal having a first data rate in response to (i) a data input signal having a second data rate and (ii) a clock signal having said second data rate;
- means for using a frequency detector for generating a second output signal having a third data rate in response to (i) said data input signal and (ii) said clock signal;
- and
- means for generating said clock signal in response to (i) said first output signal and (ii) said second output signal.
A method for clock data recovery comprising the steps of:
- (A) using a phase detector for generating a first output signal having a first data rate in response to (i) data input signal having a second data rate and (ii) a clock signal having said second data rate;
- (B) using a frequency detector for generating a second output signal having a third data rate in response to (i) said data input signal and (ii) said clock signal;
- and
- (C) generating said clock signal in response to (i) said first output signal and (ii) said second output signal.
Dependencies are inferred from the claim text.