Frequency correction loop with deadzone and hysteresis
AssigneeRenesas Electronics America Inc.
InventorRussell Fagg
Life of this patent
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Abstract
Semiconductor devices for synchronizing networks are described. A semiconductor device can include a phase lock loop of a timing circuit. The phase lock loop includes a voltage-controlled oscillator, a sub-sampling phase lock loop circuit and a frequency correction loop circuit. The frequency correction loop circuit is configured to activate a charge pump to inject a charge into the voltage-controlled oscillator based on a phase difference between a reference signal and a feedback signal being greater in magnitude than a deadzone delay parameter plus a hysteresis delay parameter and de-activate the charge pump based on the magnitude of the phase difference between the reference signal and the feedback signal falling below the deadzone delay parameter.
Claims14
A semiconductor device comprising:
- a phase lock loop of a timing circuit, the phase lock loop comprising:
- a voltage-controlled oscillator;
- a sub-sampling phase lock loop circuit;
- and
- a frequency correction loop circuit, the frequency correction loop circuit being configured to:
- activate a charge pump to inject a charge into the voltage-controlled oscillator based on a phase difference between a reference signal and a feedback signal being greater in magnitude than a deadzone delay parameter plus a hysteresis delay parameter;
- and
- de-activate the charge pump based on the magnitude of the phase difference between the reference signal and the feedback signal falling below the deadzone delay parameter, wherein the deadzone delay parameter and the hysteresis delay parameter are each separately programmable.
A frequency correction loop of a timing circuit, the frequency correction loop comprising:
- a charge pump that is configured to inject a charge into a voltage-controlled oscillator of the timing circuit;
- and
- a phase detector that is configured to control an activation of the charge pump, the phase detector comprising:
- a first latch that is configured to be set based on a reference signal to generate a first latch output signal;
- a second latch that is configured to be set based on a feedback signal from the voltage-controlled oscillator to generate a second latch output signal;
- a first latch delay circuit;
- a third latch that is configured to be set based on the first latch output signal and a first delay signal output by the first latch delay circuit;
- a second latch delay circuit;
- and
- a fourth latch that is configured to be set based on the second latch output signal and a second delay signal output by the second latch delay circuit, wherein the first and second latch delay circuits are each configured with a modifiable delay parameter that is configured to adjust a delay between a setting of the corresponding first and second latches and a setting of the corresponding third and fourth latches, wherein:
- the first latch delay circuit and the second latch delay circuit are each configured with a modifiable delay parameter, comprising a deadzone delay parameter and a hysteresis delay parameter, that is configured to adjust a delay between a setting of the corresponding first latch and second latch and a setting of the corresponding third latch and fourth latch;
- and
- the deadzone delay parameter and the hysteresis delay parameter are each separately programmable.
A semiconductor device comprising a phase detector of a timing circuit, the phase detector being configured to:
- control an activation of a charge pump of the timing circuit, the charge pump being configured to inject a charge into a voltage-controlled oscillator of the timing circuit;
- enter a set state from a reset state in response to a phase difference between a reference signal and a feedback signal exceeding a predetermined deadzone delay corresponding to the reference signal plus a predetermined hysteresis delay, the phase detector being configured to activate the charge pump when in the set state and disable the charge pump when in the reset state;
- and
- enter the reset state from the set state in response to the phase difference between the reference signal and the feedback signal being reduced to less than the predetermined deadzone delay,
- wherein the predetermined deadzone delay and the predetermined hysteresis delay are each separately programmable.
Dependencies are inferred from the claim text.