G06F 9/3865
Using deferred exception handling
Official title: {using deferred exception handling, e.g. exception flags}
G06F9/3865 (Using deferred exception handling) appears on 392 US grants and 257 published applications in this corpus.
Search patents in G06F- Granted patents
- 392
- Published applications
- 257
- Assignees
- 98
- Inventors
- 672
- Latest grant
- 11 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1985 | 1 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 4 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 5 | 0 |
| 1992 | 3 | 0 |
| 1993 | 4 | 0 |
| 1994 | 6 | 0 |
| 1995 | 9 | 0 |
| 1996 | 13 | 0 |
| 1997 | 19 | 0 |
| 1998 | 32 | 0 |
| 1999 | 14 | 0 |
| 2000 | 14 | 0 |
| 2001 | 15 | 5 |
| 2002 | 7 | 13 |
| 2003 | 11 | 13 |
| 2004 | 16 | 15 |
| 2005 | 13 | 9 |
| 2006 | 12 | 6 |
| 2007 | 4 | 4 |
| 2008 | 6 | 6 |
| 2009 | 9 | 9 |
| 2010 | 12 | 9 |
| 2011 | 7 | 12 |
| 2012 | 9 | 14 |
| 2013 | 14 | 11 |
| 2014 | 7 | 10 |
| 2015 | 11 | 11 |
| 2016 | 13 | 11 |
| 2017 | 12 | 14 |
| 2018 | 13 | 13 |
| 2019 | 11 | 10 |
| 2020 | 13 | 14 |
| 2021 | 13 | 15 |
| 2022 | 13 | 8 |
| 2023 | 9 | 11 |
| 2024 | 8 | 4 |
| 2025 | 5 | 4 |
| 2026 | 4 | 6 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Interruptible and restartable matrix multiplication instructions, processors, methods, and systems11 Aug 2026US 12,705,052 B2Intel Corporation
- Tracking near-identical memory addresses and reducing memory access requests16 Jun 2026US 12,657,156 B2Mobileye Vision Technologies Ltd.
- Analysis function for suppressing stop of execution due to an exception9 Jun 2026US 12,650,915 B2NTT, Inc.
- Dual-mode floating point processor operation7 Apr 2026US 12,596,550 B2Graphcore Limited
- Lowering Java try statements in a symbolic description language30 Dec 2025US 12,511,107 B2Oracle International Corporation
- Tracking near-identical memory addresses and reducing memory access requests17 Sep 2026US 2026/0277852 A1Mobileye Vision Technologies Ltd.
- Control flow prediction6 Aug 2026US 2026/0228005 A1Arm Limited
- Processor with delayed instruction pipeline flush23 Jul 2026US 2026/0211678 A1Rivos Inc.
- Recovery path cache11 Jun 2026US 2026/0161565 A1Intel Corporation
- Processing Vector Instructions23 Apr 2026US 2026/0111234 A1
Most cited
By later US patents
- Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched206US 5,487,156 A1996
- High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution164US 5,560,032 ASeiko Epson Corporation · 1996
- Multiprocessor digital data processing system129US 5,055,999 AKendall Square Research Corporation · 1991
- Processor architecture having out-of-order execution, speculative branching, and giving priority to instructions which affect a condition code128US 5,625,837 AHyundai Electronics America · 1997
- Processor architecture supporting multiple speculative branching123US 5,561,776 AHyundai Electronics America · 1996