Dual-mode floating point processor operation
AssigneeGraphcore Limited
InventorAlan Alexander
Life of this patent
Estimating the term…
Abstract
By providing a mode indication, an execution unit is operable to operate in two separate modes, each of which cause the execution unit to perform calculations by interpreting the same bit string (the first of the bit strings) as representing one of two different values. When operating in the first mode, the first of the bit string represents an undefined value, in other words a NaN. When operating in the second mode, the first of the bit strings represents a negative zero. Hence, the same string of bits can represent either a NaN or a negative zero depending upon the mode of operation of the processor. Since it is not necessary to reserve more than one bit string to represent these two special values, the remaining combinations of bits are available to represent other values.
Claims21
A processing device configured to interleave execution of a plurality of threads, the processing device comprising:
- an execution unit configured to execute instructions to perform operations, wherein the execution unit is configured to take at least one of a set of floating-point values as an input and produce as a result, at least one of the set of floating-point values as an output, wherein each of the set of floating-point values is represented by a respective one of a plurality of bit strings, each of the plurality of bit strings having a predefined length and provided according to a first floating-point format,
- a plurality of registers comprising a plurality of floating-point control registers and a plurality of status registers,
- wherein each of the plurality of floating-point control registers is associated with a corresponding one of the plurality of threads,
- wherein the plurality of floating-point control registers is configured to store a plurality of mode indications,
- wherein each of the plurality of mode indications indicates whether one of the operations performed by its associated thread are performed in a first mode or a second mode,
- wherein each of the plurality of status registers is associated with a corresponding one of the plurality of threads,
- wherein the execution unit is further configured to, for each of the plurality of threads:
- read the mode indication stored in an associated floating-point control register of the plurality of floating-point control registers;
- perform a first of the operations, and in response to the mode indication indicating operation in the first mode:
- determine a result of the first of the operations in dependence upon interpreting a first of the bit strings as representing an undefined value;
- raise an exception by setting an invalid operation flag in response to performing the first of the operations;
- and
- store the invalid operation flag in an associated status register from the plurality of status registers;
- and
- perform a second of the operations, and in response to the mode indication indicating operation in the second mode, determine a result of the second of the operations in dependence upon interpreting the first of the bit strings as representing a negative zero.
A method of interleaving execution of a plurality of threads in a processing device comprising a plurality of floating-point control registers and a plurality of status registers, the method comprising:
- storing a plurality of mode indications, in the plurality of floating-point control registers, wherein each of the plurality of mode indications indicates whether an associated thread of the plurality of threads operates according to a first mode or a second mode;
- executing instructions to perform operations, wherein each of the operations takes a floating-point input represented by a bit string of a plurality of bit strings and produces, as a result, a floating-point output represented by another bit string of the plurality of bit strings, wherein each bit string of the plurality of bit strings has a predefined length and conforms to a first floating-point format;
- for a first of the plurality of threads:
- reading a first mode indication from an associated floating-point control register of the plurality of floating-point control registers;
- performing a first of the operations in the first mode indicated by the first mode indication, comprising:
- determining a result of the first of the operations in dependence upon interpreting a first of the bit strings as representing an undefined value;
- raising an exception by setting an invalid operation flag in response to performing the first of the operations;
- and
- storing the invalid operation flag in an associated status register from the plurality of status registers;
- and
- for a second of the plurality of threads:
- reading a second mode indication from an associated floating-point control register of the plurality of floating-point control registers;
- performing a second of the operations in the second mode indicated by the second mode indication, comprising determining a result of the second of the operations in dependence upon interpreting the first of the bit strings as representing a negative zero.
A non-transitory computer readable medium storing a computer program comprising a set of computer executable instructions, which when executed by a processing device comprising a plurality of floating-point control registers and a plurality of status registers cause a method of interleaving execution of a plurality of threads to be performed, the method comprising:
- storing a plurality of mode indications, in the plurality of floating-point control registers, wherein each of the plurality of mode indications indicates whether an associated thread of the plurality of threads operates according to a first mode or a second mode;
- executing instructions to perform operations, wherein each of the operations takes a floating-point input represented by a bit string of a plurality of bit strings and produces, as a result, a floating-point output represented by another bit string of the plurality of bit strings, wherein each bit string of the plurality of bit strings has a predefined length and conforms to a first floating-point format;
- for each of the plurality of threads:
- reading the mode indication from an associated floating-point control register of the plurality of floating-point control registers;
- performing a first of the operations, and in response to the mode indication indicating operation in the first mode:
- determining a result of a first of the operations in dependence upon interpreting a first of the bit strings as representing an undefined value;
- raising an exception by setting an invalid operation flag in response to performing the first of the operations;
- and
- storing the invalid operation flag in an associated status register from the plurality of status registers;
- and
- performing a second of the operations, and in response to the mode indication indicating operation in the second mode, determining a result of the second of the operations in dependence upon interpreting the first of the bit strings as representing a negative zero.
Dependencies are inferred from the claim text.