Processor architecture having out-of-order execution, speculative branching, and giving priority to instructions which affect a condition code

A data processing system for processing information in response to an ordered series of instructions including instructions that control arithmetic operations on the information and a plurality of branch instructions, each branch instruction accepting input from a stored condition code, the data processing system comprising:

• a register unit that stores information;
• a fetch unit that continuously fetches instructions from the series of instructions;
• a shelver coupled to the fetch unit to receive fetched instructions and to store multiple such instructions, wherein each instruction stored within the shelver is assigned a priority, and wherein such instruction stored within the shelver is stored with a sequential instruction identifier assigned in the order fetched, the sequential instruction identifier being an indicator of seniority within the shelver;
• a scheduler coupled to the shelver that continuously selects instructions in the shelver for which all information required for execution is available in the register unit or the shelver for execution and that issues those instructions for execution in an order in accordance with the priority of each instruction and a seniority of each instruction within the shelver as indicated by said sequential instruction identifier;
• an arithmetic unit coupled to the scheduler that perform operations on information in the register unit or shelver in response to instructions supplied from the shelver to generate execution results;
• a branch predictor that predicts a speculative sequence of instructions following each branch instruction, wherein the fetch unit fetches instructions in accordance with the speculative sequence;
• an evaluator that evaluates each branch instruction subsequent to the execution of a last instruction that affects the stored condition code that is the input to the branch instruction;
• an incorrect branch repairer that, upon detection of an incorrectly predicted branch instruction by the evaluator, repairs effects of the incorrectly predicted branch instruction and all instructions of the speculative sequence following the branch instruction;
• and wherein
• the shelver assigns a higher priority to instructions that affect the stored condition code,
• whereby the assignment of high priority to instructions that affect the stored condition code accelerates detection and repair of effects of incorrectly predicted branches.