Processor architecture supporting multiple speculative branching
AssigneeHyundai Electronics America
InventorsValeri Popescu, Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner
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AssigneeHyundai Electronics America
InventorsValeri Popescu, Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner
Estimating the term…
A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.
A data processing system that performs operations responsive to a program including a plurality of instructions, the instructions including arithmetic instructions at least a first and second test instruction and at least a first and second branch instruction that determine an intended sequence of execution of the instructions within the program responsive to results of the first and second test instructions respectively, the system comprising:
A data processing system that performs operations responsive to a program including a plurality of instructions, the instructions including at least a first and second test instruction and at least a first and second branch instruction that determine an intended sequence of execution of the instructions within the program responsive to results of the first and second test instructions respectively, the system comprising:
A data processing system capable of executing a sequence of instructions, the sequence including a plurality of branch instructions, each branch instruction of the plurality associated with a test instruction, the data processing system comprising:
Dependencies are inferred from the claim text.