G06F 9/264
Microinstruction selection based on results of processing
Official title: {Microinstruction selection based on results of processing}
G06F9/264 (Microinstruction selection based on results of processing) appears on 242 US grants and 74 published applications in this corpus.
Search patents in G06F- Granted patents
- 242
- Published applications
- 74
- Assignees
- 84
- Inventors
- 347
- Latest grant
- 30 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 6 | 0 |
| 1977 | 9 | 0 |
| 1978 | 4 | 0 |
| 1979 | 7 | 0 |
| 1980 | 3 | 0 |
| 1981 | 5 | 0 |
| 1982 | 6 | 0 |
| 1983 | 7 | 0 |
| 1984 | 11 | 0 |
| 1985 | 6 | 0 |
| 1986 | 8 | 0 |
| 1987 | 5 | 0 |
| 1988 | 7 | 0 |
| 1989 | 13 | 0 |
| 1990 | 9 | 0 |
| 1991 | 6 | 0 |
| 1992 | 7 | 0 |
| 1993 | 7 | 0 |
| 1994 | 3 | 0 |
| 1995 | 6 | 0 |
| 1996 | 5 | 0 |
| 1997 | 7 | 0 |
| 1998 | 7 | 0 |
| 1999 | 3 | 0 |
| 2000 | 2 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 1 |
| 2003 | 2 | 2 |
| 2004 | 2 | 5 |
| 2005 | 5 | 5 |
| 2006 | 2 | 2 |
| 2007 | 2 | 2 |
| 2008 | 1 | 2 |
| 2009 | 3 | 5 |
| 2010 | 3 | 2 |
| 2011 | 6 | 2 |
| 2012 | 1 | 1 |
| 2013 | 0 | 28 |
| 2014 | 16 | 1 |
| 2015 | 25 | 1 |
| 2016 | 2 | 1 |
| 2017 | 1 | 1 |
| 2018 | 2 | 1 |
| 2019 | 0 | 1 |
| 2020 | 1 | 3 |
| 2021 | 1 | 1 |
| 2022 | 1 | 1 |
| 2023 | 3 | 1 |
| 2024 | 1 | 1 |
| 2025 | 1 | 1 |
| 2026 | 2 | 3 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Configurable multi-protocol data extraction device30 Jun 2026US 12,669,995 B1Tractian Technologies Inc
- Computing chip and instruction processing method to access source operands in private registers using a relative distance index21 Apr 2026US 12,608,200 B2Huawei Technologies Co., Ltd.
- Control of instruction issue based on issue groups24 Jun 2025US 12,340,216 B1Arm Limited
- Instruction writing method and apparatus, and network device25 Jun 2024US 12,020,026 B2Huawei Technologies Co., Ltd.
- Accelerator controller for inserting template microcode instructions into a microcode buffer to accelerate matrix operations5 Dec 2023US 11,836,488 B2Telefonaktiebolaget LM Ericsson (publ)
- Autopredication of Tail-Nested Region and Loop Many-Trip Count Region11 Jun 2026US 2026/0161393 A1
- Apparatus and Method for Execution and Retirement of Auto-Predicated Program Code Regions11 Jun 2026US 2026/0161394 A1
- Data prefetching based on both intra-tile and inter-tile stride information7 May 2026US 2026/0126996 A1Intel Corporation
- Control of instruction issue based on issue groups26 Jun 2025US 2025/0208863 A1Arm Limited
- Computing chip and instruction processing method19 Dec 2024US 2024/0419443 A1Huawei Technologies Co., Ltd.
Most cited
By later US patents
- Hierarchical priority branch handling for parallel execution in a parallel processor218US 4,833,599 AMultiflow Computer, Inc. · 1989
- System with plurality of processing elememts each generates respective instruction based upon portions of individual word received from a crossbar switch169US 5,055,997 AU. S. Philips Corporation · 1991
- Digital camera system containing a VLIW vector processor133US 6,879,341 B1Silverbrook Research Pty Ltd · 2005
- Digital camera having functionally interconnected image processing elements123US 7,701,506 B2Silverbrook Research Pty Ltd · 2010
- Processor with accelerated array access bounds checking118US 6,014,723 ASun Microsystems, Inc. · 2000