Computing chip and instruction processing method to access source operands in private registers using a relative distance index

An instruction processing method, applied to a computing chip that uses a superscalar processor architecture, wherein the computing chip comprises a plurality of registers, and the plurality of registers comprise a general purpose register and a plurality of private registers, wherein the method comprises:

• obtaining a plurality of microinstructions used to implement a computing task;
• parsing a first microinstruction in the plurality of microinstructions to obtain a parsing result;
• obtaining a source operand in a first register in the plurality of registers based on the parsing result, wherein the source operand comprises an execution result of a second microinstruction referenced by the first microinstruction, and, when the first register comprises the private register, the parsing result comprises a relative distance index indicating a relative distance between the first microinstruction and the second microinstruction;
• determining, based on the parsing result and the source operand, an execution result of the first microinstruction;
• when the first microinstruction is a jump instruction, updating, to an idle state, a private register occupied by each microinstruction in a preset quantity of microinstructions before the jump instruction, wherein the preset quantity comprises an integer greater than or equal to 1;
• and
• storing the execution result of the first microinstruction in a second register that is in the plurality of registers and that is different from the first register, and performing the parsing the first microinstruction in the plurality of microinstructions to obtain a parsing result until the computing task is completed, wherein:
• when the first microinstruction comprises a before-jump instruction, the second register comprises the general purpose register, the before-jump instruction comprises a microinstruction that is in the plurality of microinstructions and that is executed before the jump instruction and whose execution result is referenced by an after-jump instruction, and the after-jump instruction comprises a microinstruction that is executed after the jump instruction;
• or
• when the first microinstruction comprises a microinstruction other than a storage instruction in the plurality of microinstructions, the second register comprises any private register in the plurality of private registers.

An electronic device, comprising:

• a computing chip, wherein the computing chip has a superscalar processor architecture and comprises a plurality of registers and an instruction processing unit, the plurality of registers are separately coupled to the instruction processing unit, and the plurality of registers comprise a general purpose register and a plurality of private registers that are separately coupled to the general purpose register;
• at least one processor;
• and
• a memory, configured to store one or more programs, wherein:
• when the one or more programs are executed by the at least one processor, the at least one processor is enabled to implement an instruction processing method comprising:
• obtaining a plurality of microinstructions used to implement a computing task;
• parsing a first microinstruction in the plurality of microinstructions to obtain a parsing result;
• obtaining a source operand in a first register in the plurality of registers based on the parsing result, wherein the source operand comprises an execution result of a second microinstruction referenced by the first microinstruction, and, when the first register comprises the private register, the parsing result comprises a relative distance index indicating a relative distance between the first microinstruction and the second microinstruction;
• determining, based on the parsing result and the source operand, an execution result of the first microinstruction;
• when the first microinstruction is a jump instruction, updating, to an idle state, a private register occupied by each microinstruction in a preset quantity of microinstructions before the jump instruction, wherein the preset quantity comprises an integer greater than or equal to 1;
• and
• storing the execution result of the first microinstruction in a second register that is in the plurality of registers and that is different from the first register, and performing the parsing the first microinstruction in the plurality of microinstructions to obtain a parsing result until the computing task is completed, wherein:
• when the first microinstruction comprises a before-jump instruction, the second register comprises the general purpose register, the before-jump instruction comprises a microinstruction that is in the plurality of microinstructions and that is executed before the jump instruction and whose execution result is referenced by an after-jump instruction, and the after-jump instruction comprises a microinstruction that is executed after the jump instruction;
• or
• when the first microinstruction comprises a microinstruction other than a storage instruction in the plurality of microinstructions, the second register comprises any private register in the plurality of private registers.