Accelerator controller for inserting template microcode instructions into a microcode buffer to accelerate matrix operations

A non-transitory computer readable storage medium, having thereon a computer program comprising program instructions which, when executed by a processing unit, cause a controller to execute a program comprising a sequence of functions on an accelerator with a pipelined architecture comprising a microcode buffer, wherein each function comprises a sequence of operations and wherein each operation is represented by a template comprising a sequence of microcode instructions to be executed during a set of clock cycles for utilization of available resources in the accelerator by performing operations comprising:

• executing a function of the program as a sequence of operations, wherein the sequence of operations is represented by a sequence of templates comprising microcode instructions, wherein the microcode instructions specify addresses, registers, and timing requirements related to each operation in the sequence of operations,
• determining, based on the microcode instructions in the template, whether the template is non-colliding with previously inserted templates in the microcode buffer to solve resource dependencies,
• determining, based on the microcode instructions in the template specifying addresses, whether data in local memory will be referenced before all previously inserted templates have taken effect to solve data dependencies,
• determining, based on the microcode instructions in the template specifying registers, whether registers will be referenced before all previously inserted templates in the microcode buffer have taken effect to solve register dependencies,
• when it is determined that the template fits, that resources are available, that local data memory accesses will not collide, and that register accesses will not collide:
• creating a sequence of microcode instructions in the template fulfilling the timing requirements on the fly, and
• inserting the template into the microcode buffer for execution of the created sequence of microcode instructions in the template, wherein the template comprises sequences of microcode instructions where each microcode instruction comprises instructions for one clock cycle.

A controller to execute a program comprising a sequence of functions on an accelerator with a pipelined architecture comprising a microcode buffer, wherein the controller is programmable with the sequence of functions, wherein each function comprises a sequence of operations, and wherein each operation is represented by a template comprising a sequence of microcode instructions to be executed during a set of clock cycles for utilization of available resources in the accelerator, the controller to:

• execute a function of the program as a sequence of operations, wherein the sequence of operations is represented by a sequence of templates comprising microcode instructions, wherein the microcode instructions specify addresses, registers, and timing requirements related to each operation in the sequence of operations,
• determine, based on the microcode instructions in the template, whether the template is non-colliding with previously inserted templates in the microcode buffer to solve resource dependencies,
• determine, based on the microcode instructions in the template specifying addresses, whether data in local memory will be referenced before all previously inserted templates in the microcode buffer have taken effect to solve data dependencies,
• determine, based on the microcode instructions in the template specifying registers, whether registers will be referenced before all by previously inserted templates in the microcode buffer have taken effect to solve register dependencies,
• responsive to determination that the template fits, that resources are available, that local data memory accesses will not collide, and that register accesses will not collide:
• create a sequence of microcode instructions in the template fulfilling the timing requirements on the fly, and
• insert the template into the microcode buffer for execution of the created sequence of microcode instructions in the template, wherein the template comprises sequences of microcode instructions where each microcode instruction comprises instructions for one clock cycle.