G06F 7/764
Masking
Official title: {Masking}
G06F7/764 (Masking) appears on 150 US grants and 102 published applications in this corpus.
Search patents in G06F- Granted patents
- 150
- Published applications
- 102
- Assignees
- 80
- Inventors
- 337
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 2 | 0 |
| 1979 | 2 | 0 |
| 1980 | 0 | 0 |
| 1981 | 1 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 1 | 0 |
| 1986 | 1 | 0 |
| 1987 | 1 | 0 |
| 1988 | 3 | 0 |
| 1989 | 1 | 0 |
| 1990 | 3 | 0 |
| 1991 | 4 | 0 |
| 1992 | 2 | 0 |
| 1993 | 2 | 0 |
| 1994 | 1 | 0 |
| 1995 | 3 | 0 |
| 1996 | 3 | 0 |
| 1997 | 7 | 0 |
| 1998 | 10 | 0 |
| 1999 | 6 | 0 |
| 2000 | 2 | 0 |
| 2001 | 1 | 1 |
| 2002 | 8 | 3 |
| 2003 | 10 | 4 |
| 2004 | 5 | 2 |
| 2005 | 1 | 3 |
| 2006 | 3 | 2 |
| 2007 | 0 | 1 |
| 2008 | 3 | 5 |
| 2009 | 1 | 2 |
| 2010 | 2 | 3 |
| 2011 | 3 | 3 |
| 2012 | 2 | 3 |
| 2013 | 4 | 2 |
| 2014 | 5 | 4 |
| 2015 | 1 | 4 |
| 2016 | 5 | 5 |
| 2017 | 3 | 2 |
| 2018 | 2 | 2 |
| 2019 | 3 | 5 |
| 2020 | 4 | 7 |
| 2021 | 3 | 8 |
| 2022 | 2 | 6 |
| 2023 | 7 | 8 |
| 2024 | 8 | 7 |
| 2025 | 5 | 5 |
| 2026 | 3 | 5 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Multiplication with data protection29 Sep 2026US 12,748,571 B2STMicroelectronics (Rousset) SAS
- Secure computation system, secure computation server apparatus, secure computation method, and secure computation program19 May 2026US 12,634,142 B2NEC Corporation
- Method for calculating a transition from a Boolean masking to an arithmetic masking17 Mar 2026US 12,578,927 B2Giesecke+Devrient Epayments GmbH
- Device and methods for functional descriptor-based DMA controller9 Dec 2025US 12,493,570 B2Microchip Technology Incorporated
- Reducing power consumption in integrated circuits11 Nov 2025US 12,468,507 B1Amazon Technologies, Inc.
- Direct memory access circuit with masking conversions3 Sep 2026US 2026/0259844 A1
- Method of generating an output binary word from an input binary word, method of performing an arithmetic operation on an input binary word associated to an output binary word, corresponding computer program product and devices27 Aug 2026US 2026/0252309 A1Nagravision Sarl
- Processor23 Apr 2026US 2026/0111230 A1
- Dynamic element matching encoder providing a quasi-constant number of transitions as a function of a control word5 Feb 2026US 2026/0037216 A1Infineon Technologies AG
- Security Device1 Jan 2026US 2026/0003573 A1
Most cited
By later US patents
- Microprocessors194US 6,658,578 B1Texas Instruments Incorporated · 2003
- 32-Bit extended function arithmetic-logic unit on a single chip141US 4,785,393 AAdvanced Micro Devices, Inc. · 1988
- Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU125US 5,781,457 AExponential Technology, Inc. · 1998
- Multiplier accumulator circuits96US 6,571,268 B1Texas Instruments Incorporated · 2003
- Circuits for accessing a variable width data bus with a variable width data field92US 4,667,305 AInternational Business Machines Corporation · 1987