US 5,781,457 AGranted

Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU

AssigneeExponential Technology, Inc.

InventorsEarl T. Cohen, James S. Blomgren, David E. Richter

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Abstract

A Boolean logic unit (BLU) features a vectored mux. Boolean instructions are executed by applying operands to the select inputs but truth-table signals to the data inputs. Merge and mask operations are performed by reversing the connection and inputting the operands to the data inputs but applying a merge mask to the select inputs. A byte-spreader copies byte or 16-bit operands to 32-bits before being rotated and merged by the vectored mux. A rotator is used to rotate an operand before being applied to the data input of the vectored mux so that compound rotate-merge operations can be executed in a single step through the vectored mux. A carry flag may also be merged in during a multi-step bit-test instruction. Complex CISC instructions such as rotate-through-carry and shift-double are executed in multiple steps on the vectored mux. Intermediate results are stored in the multiplier-quotient temporary registers which are normally used for multiply and divide instructions. A RISC ALU using the vectored mux BLU is modified only slightly to support execution of CISC instructions. Merge, mask, rotate, shift, and Boolean operations of both RISC and CISC instruction sets are executed in the same ALU because of the inherent flexibility of the vectored mux architecture.

Claims16

Dependent claims

A logic-instruction execution unit for executing Boolean operations and merge operations, the logic-instruction execution unit comprising:

a vectored mux for outputting a result of a Boolean operation or a merge operation, the vectored mux comprising a plurality of individual mux cells, each mux cell having data inputs and select control inputs and an output driving one bit-position of the result, the select control inputs controlling which data input is coupled to drive the output independently of other data inputs;
a first operand input comprising a plurality of electrical signals representing a first operand;
a second operand input comprising a plurality of electrical signals representing a second operand;
operand-spread means, receiving the first operand input, for extending the first operand from a reduced-width operand to a full-width operand by duplicating the reduced-width operand to fill bit-positions in a full-width operand beyond the reduced-width operand, the operand-spread means outputting a spread first operand to a first data input of the vectored mux when the first operand is a reduced-width operand;
Boolean control means for applying the first operand input and the second operand input to the select control inputs of the vectored mux when a Boolean operation is executed;
truth-table inputs comprising electrical signals representing at truth table for the Boolean operation, the truth-table inputs varying for different Boolean operations;
the Boolean control means including means for applying the truth-table inputs to the data inputs of the vectored mux when a Boolean operation is executed;
merge control means for applying the spread first operand to the first data input on the vectored mux and for applying the second operand input to a second data input on the vectored mux when a merge operation is executed;
a mask generator for generating a mask indicating a first portion of the result from the first operand and a second portion of the result from the second operand, the first portion and the second portion not overlapping;
the merge control means including means for applying the mask to a select control input of the vectored mux when a merge operation is executed, wherein the mask causes the vectored mux to select the first portion of the first operand applied to the first data input and the second portion of the second operand applied to the second data input,
whereby the vectored mux executes both merge operations and Boolean operations, the operands applied to the data inputs for merge operations but applied to the select control inputs for Boolean operations.

8 more elements

A central processing unit (CPU) having an arithmetic-logic-unit (ALU) for executing integer instructions from a first instruction set and from a second instruction set, wherein the ALU comprises:

a first operand input;
a second operand input;
a byte-spreader for copying a byte-operand to a full width of the ALU;
a result output;
an adder for performing add and subtract operations on the first and second operand inputs, the adder outputting a sum as the result output;
a Boolean-logic unit for performing Boolean, merge, rotate, and shift operations, the Boolean-logic unit comprising:
a vectored mux having a plurality of multiplexer cells each having data inputs, a first select input and a second select input, and output for outputting one bit-position of the result output, each multiplexer cell selecting one of the data inputs as the result output in response to the first and second select inputs;
truth-table means for applying electrical signals representing a truth-table of a Boolean-logic function being executed to the data inputs of the vectored mux;
first select means for applying the second operand input to the first select inputs of the vectored mux when a Boolean operation is being executed, but applying a constant signal to the first select inputs when a Boolean operation is not being executed;
mask generator means for generating a mask indicating which bit-positions of the first operand input are output to the result output and which bit-positions of the first operand input are not output to the result output;
second select means for applying the first operand input to the second select inputs of the vectored mux when a Boolean operation is being executed, but applying the mask to the second select inputs when a Boolean operation is not being executed;
a shifter for shifting and rotating the first operand input to produce a shifted first operand when a rotate or shift operation is being executed;
first data select means, coupled to the shifter and the truth-table means, for outputting one of the truth-table signals to a data input of the vectored mux when a Boolean operation is being executed but for outputting the shifted first operand to a data input of the vectored mux when a Boolean operation is not being executed;
second data select means, coupled to the second operand input and the truth-table means, for outputting a second one of the truth-table signals to a second data input of the vectored mux when a Boolean operation is being executed but for outputting the second operand input to the second data input of the vectored mux when a Boolean operation is not being executed;
whereby the Boolean-logic unit executes Boolean-logic operations and merge, rotate, and shift operations.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/649,116Filed 14 May 1996 · continuation in part
Priority: 8 Mar 1994
Granted: 14 Jul 1998
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 7/764
Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data: masking
G06F 7/575
Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556…
G06F 7/762
Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data: having at…
G06F
Computing and data processing

Family

Serial207,751Parent of this continuation · filed 8 Mar 1994
Serial444,814Parent of this continuation-in-part · filed 18 May 1995
Serial609,908Parent of this continuation-in-part · filed 29 Feb 1996
US 5,497,341 AParent of this continuation-in-part
US 4,442,577 AParent of this continuation
US 5,781,457 AThis patent

From the US filing history. Foreign family members aren’t listed.