US 6,658,578 B1 · Microprocessors

Abstract

A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address/data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

Claims22

Dependent claims

A digital system comprising a programmable processor with variable instruction length, wherein the processor comprises:

an instruction buffer unit, a program flow control unit with a decode mechanism, an address/data flow unit, a data computation unit, dual multiply-accumulate blocks, with multiple interconnecting busses connected there between and to a memory interface unit, the memory interface unit connected in parallel to a data memory and an instruction memory;
wherein the instruction buffer is operable to buffer single and compound instructions pending execution thereof;
wherein the decode mechanism is operable to decode instructions from the instruction buffer, including compound instructions and soft dual memory instruction;
wherein the program flow control unit is operable to conditionally execute an instruction decoded by the decode mechanism or to repeatedly execute an instruction or sequence of instruction decoded by the decode mechanism;
wherein the address/data flow unit is operable to perform bit field processing and to perform various addressing modes, including circular buffer addressing;
wherein the processor further comprises a multistage execution pipeline connected to the program flow control unit, the execution pipeline having pipeline protection features;
an emulation and code debugging facility with support for cache analysis, cache benchmarking, and cache coherence management connected to the program flow control unit, to the address/data unit, and to the data computation unit;
and
wherein various functional modules can be separately powered down to conserve power.

6 more elements

A digital system comprising a programmable processor, wherein the processor comprises:

a plurality of clock domains, wherein a least some of the plurality of clock domains are operable to enter into a low power state;
power down control circuitry connected to certain of the plurality of clock domains;
the power down control circuitry operable to cause selected ones of the plurality of clock domains to enter a low power state;
and
error circuitry connected to the power down control circuitry;
the error circuitry operable to inhibit at least one of the selected ones of the plurality of clock domains from entering a low power state, wherein the error circuitry is operable to interrupt the processor when the error circuitry inhibits at least one of the selected ones of the plurality of clock domains from entering a low power state.

3 more elements

Dependencies are inferred from the claim text.

Microprocessors

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Microprocessors

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Abstract

Claims22