US 4,785,393 AGranted

32-Bit extended function arithmetic-logic unit on a single chip

AssigneeAdvanced Micro Devices, Inc.

InventorsPaul P. Chu, Deepak R. Mithani, Sanjay Iyer

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Abstract

A one-chip, integrated-circuit, 32-bit bipolar arithmetic-logic unit (ALU) capable of performing complex operations on selected one, two, three, or four 8-bit bytes or selected contiguous bits of the operands in a single clock cycle. The ALU has three 32-bit inputs consisting of two data word operands and a mask; operand with shifters provided at one of the operand input, the mask input and at the ALU output so that three operands can be simultaneously received, shifted, masked, combined, and the result shifted in a single instruction cycle. Bit positions which are not selected to take part in an ALU operation pass unaffected to the outputs from one of the data word inputs. A swap multiplexer is present at the data word inputs to afford interchanging of these inputs before processing by the ALU. A moving arithmetic cell is employed within the ALU which can be appended to the selected high-order byte during a multiplication operation and the ALU is composed of sixteen two-bit arithmetic cells which generate four conditional sums to which a last minute correction is made based on the carry in to the cell from the adjoining cell. A one-bit upshift or a two-bit downshift of the result can be made during the same clock cycle to implement the division and multiplication algorithms used by the ALU. A terminal pin is provided to permit selection of a borrow or a carry made to be utilized during subtractions.

Claims16

Dependent claims

In a microprocessor, including memory means for storing a plurality of multi-bit data words arranged into 8 bit "bytes" and sequencer means connected to said memory means for cyclically generating data word memory addresses and generating data processor instructions from a set each instruction of which comprises a word having a plurality of bits arranged into fields, containing at least an operation code field defining the instruction and a data specification field defining the portion of the data words to be processed during the execution of the said instruction, a data processor device connected to said memory means and responsive to said instruction words for receiving said multi-bit-data words located at said generated addresses and processing selectable portions of said multi-bit data words, said data processor device comprising:

decoder means for receiving said instruction words and for generating therefrom a plurality of control signals;
mask generation and shifting means connected to said decoder means and responsive to said decoder control signals for selectively generating and selectively upshifting a multi-bit word generating thereby a multi-bit mask word comprising a selectable portion of ZERO bits and a remaining portion of ONE bits;
and
arithmetic-logic means connected to said decoder means and responsive to said decoder control signals having first and second operand inputs connected to said storage means for receiving said multi-bit data words at said first and second operand inputs and having a third operand input connected to said mask generation means for receiving said multi-bit mask word at said third operand input and executing in a single processor clock cycle selectable arithmetic and logic operations on said selected portions of said data words at said first and second operand inputs specified in said operation code field of said processor instruction and generating at an output of said arithmetic-logic means a multi-bit word comprising within the portion corresponding to said ZERO bits within said mask word, the result of said operation on said selected portions of said data words at said first and second operand inputs corresponding to those bit positions in which said mask bits are ZEROs and, within the remaining portion corresponding to said ONE bits within said mask word, that portion of either said data word at said first or second operand input corresponding to said ONE bits within said mask word, depending on said operation code field of said processor instruction.

1 more element

In a microprocessor, including memory means for storing a plurality of words having a plurality of bits arranged into fields, containing at least a data field portion and a parity field portion, a data processor device connected to said memory means for receiving said words and processing said data field portion thereof and generating an output word having a plurality of bits arranged into fields, containing at least a data field portion and a parity field portion, the data processor device including;

parity validation means deployed on each path connecting said memory means and said data processor for generating a parity error signal whenever the number of ONE bits within said parity field portion of said word communicated on said path differs from a predetermined value;
and
parity generation means for generating said parity field portion of said output word wherein said number of ONE bits within said parity field portion bears a predetermined relationship to said plurality of bits within said data field portion,
further including comparator means receiving at a first plurality of inputs said plural-bit processor output word, containing said data field and parity field portions, and said parity error signal generated by said (first) processor device and receiving at a second plurality of inputs a second plural-bit output word generate by a second said processor device, operating in parallel with said first processor device, containing a second data field and parity field portions, and a second parity error signal, for issuing a signal indicating the outcome of testing for equality the respective bit positions of said first and second processor output words and said first and second parity error signals.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 06/628,921Filed 9 Jul 1984
Granted: 15 Nov 1988
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 7/764
Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data: masking
G06F 7/57
Using non-contact-making devices, e.g. tube, solid state device; using unspecified devices: arithmetic logic units [ALU], i.e. arrangements or…
G06F 7/4991
Exception handling: overflow or underflow
G06F 2207/3816
Devices capable of handling different types of numbers: accepting numbers of variable word length