G06F 7/762
Having at least two separately controlled rearrangement levels
Official title: {having at least two separately controlled rearrangement levels, e.g. multistage interconnection networks (G06F7/764 - G06F7/768 take precedence)}
G06F7/762 (Having at least two separately controlled rearrangement levels) appears on 125 US grants and 75 published applications in this corpus.
Search patents in G06F- Granted patents
- 125
- Published applications
- 75
- Assignees
- 57
- Inventors
- 189
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 2 | 0 |
| 1978 | 0 | 0 |
| 1979 | 2 | 0 |
| 1980 | 1 | 0 |
| 1981 | 2 | 0 |
| 1982 | 0 | 0 |
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 1 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 1 | 0 |
| 1989 | 2 | 0 |
| 1990 | 3 | 0 |
| 1991 | 3 | 0 |
| 1992 | 2 | 0 |
| 1993 | 0 | 0 |
| 1994 | 2 | 0 |
| 1995 | 5 | 0 |
| 1996 | 1 | 0 |
| 1997 | 4 | 0 |
| 1998 | 1 | 0 |
| 1999 | 2 | 0 |
| 2000 | 2 | 0 |
| 2001 | 3 | 2 |
| 2002 | 7 | 4 |
| 2003 | 8 | 5 |
| 2004 | 9 | 4 |
| 2005 | 4 | 4 |
| 2006 | 5 | 3 |
| 2007 | 2 | 3 |
| 2008 | 2 | 3 |
| 2009 | 3 | 2 |
| 2010 | 1 | 2 |
| 2011 | 1 | 1 |
| 2012 | 3 | 1 |
| 2013 | 1 | 2 |
| 2014 | 1 | 2 |
| 2015 | 2 | 0 |
| 2016 | 3 | 0 |
| 2017 | 1 | 0 |
| 2018 | 0 | 1 |
| 2019 | 1 | 3 |
| 2020 | 2 | 11 |
| 2021 | 4 | 2 |
| 2022 | 5 | 9 |
| 2023 | 3 | 1 |
| 2024 | 7 | 5 |
| 2025 | 5 | 3 |
| 2026 | 3 | 2 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Tiled switch matrix data permutation circuit6 Oct 2026US 12,754,716 B2Groq, Inc.
- Systems, methods, and apparatuses for tile transpose9 Jun 2026US 12,650,839 B2Intel Corporation
- Systems, methods, and apparatuses for tile store27 Jan 2026US 12,536,020 B2Intel Corporation
- Systems, methods, and apparatuses for dot production operations27 May 2025US 12,314,717 B2Intel Corporation
- Neural network operation method and apparatus with mapping orders27 May 2025US 12,314,843 B2Samsung Electronics Co., Ltd.
- Systems, methods, and apparatuses for tile transpose24 Sep 2026US 2026/0288459 A1Intel Products IP LLC
- Sparse compute-in-memory tensor core28 May 2026US 2026/0147852 A1Moffett International Co., Limited
- Systems, methods, and apparatuses for tile transpose10 Apr 2025US 2025/0117221 A1Intel Corporation
- Systems, methods, and apparatuses for tile matrix multiplication and accumulation10 Apr 2025US 2025/0117222 A1Intel Corporation
- Systems, methods, and apparatuses for tile load2 Jan 2025US 2025/0004716 A1Intel Corporation
Most cited
By later US patents
- Microprocessors194US 6,658,578 B1Texas Instruments Incorporated · 2003
- Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU125US 5,781,457 AExponential Technology, Inc. · 1998
- Autonomic string-manipulation system97US 4,286,330 A1981
- Multiplier accumulator circuits96US 6,571,268 B1Texas Instruments Incorporated · 2003
- Multi-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic mode90US 5,471,628 AInternational Business Machines Corporation · 1995