Systems, methods, and apparatuses for dot production operations

A system comprising:

• a memory;
• and
• a processor coupled with the memory, the processor comprising:
• a first one or more registers to store a first M row by K column (M×K) matrix,
• a second one or more registers to store a second K row by N column (K×N) matrix,
• a third one or more registers to store a third M row by N column (M×N) matrix,
• decode circuitry to decode a single instruction, the single instruction having fields to indicate the first (M×K) matrix as a first operand for execution of the single instruction, the second K (K×N) matrix as a second operand for execution of the single instruction, and the third (M×N) matrix as a third operand for execution of the single instruction, the first M×K matrix having data elements of a first size, the second K×N matrix having data elements of the first size, and the third M×N matrix having data elements of a second size four times the first size;
• and
• execution circuitry, coupled with the decode circuitry, the execution circuitry to perform operations corresponding to the instruction, including to:
• for each row of the first M×K matrix, and each column of the second K×N matrix:
• generate a dot-product from all data elements of the row of the first M×K matrix and all data elements of the column of the second K×N matrix;
• and
• accumulate the dot-product with a data element from a corresponding row and a corresponding column of the third M×N matrix.

A method comprising:

• decoding a single instruction having fields indicating a first one or more registers to store a first M row by K column (M×K) matrix as a first operand for execution of the single instruction, a second one or more registers to store a second K row by N column (K×N) matrix as a second operand for execution of the single instruction, and a third one or more registers to store a third M row by N column (M×N) matrix as a third operand for execution of the single instruction, the first M×K matrix having data elements of a first size, the second K×N matrix having data elements of the first size, and the third M×N matrix having data elements of a second size four times the first size;
• and
• performing operations corresponding to the instruction, including:
• for each row of the first M×K matrix, and each column of the second K×N matrix:
• generating a dot-product from all data elements of the row of the first M×K matrix and all data elements of the column of the second K×N matrix;
• and
• accumulating the dot-product with a data element from a corresponding row and a corresponding column of the third M×N matrix.

An apparatus comprising:

• a plurality of memory controllers;
• a bus controller;
• programmable configuration storage to store configuration information for a first matrix, a second matrix, and a third matrix, the configuration information including a first value corresponding to a first number of rows for the first matrix, a second value corresponding to a second number of columns for the first matrix, a third value corresponding to a third number of rows for the second matrix, a fourth value corresponding to a fourth number of columns for the second matrix, a fifth value corresponding to a fifth number of rows for the third matrix, a sixth value corresponding to a sixth number of columns for the third matrix, and a start row value corresponding to a row of a corresponding matrix at which to restart execution of at least one of a plurality of matrix instructions;
• decode circuitry to decode the plurality of matrix instructions, including a single instruction to perform dot-product and accumulation, the single instruction having a first operand to specify a first one or more registers, a second operand to specify a second one or more registers, and a third operand to specify a third one or more registers;
• and
• execution circuitry, coupled to the programmable configuration storage and the decode circuitry, the execution circuitry to perform one or more operations corresponding to the single instruction, including:
• performing dot-products on elements of the second matrix from the second one or more registers and elements of the third matrix from the third one or more registers to generate one or more resulting elements, and
• accumulating the one or more resulting elements into the first matrix in the first one or more registers.