Systems, methods, and apparatuses for tile store

A method comprising:

• storing a configuration value for tiles in a register;
• decoding an instruction, the instruction having a field identifying a plurality of non-consecutive vector registers, a field identifying a register to store a base, and a field identifying a register to store an index, wherein the plurality of non-consecutive vector registers store 64-bit data elements, and wherein the plurality of non-consecutive vector registers have a single-instruction, multiple-data (SIMD) dimension based on the configuration value for the tiles;
• and
• performing operations corresponding to the instruction, including storing the 64-bit data elements from the plurality of non-consecutive vector registers to destination memory locations generated using the base and the index.

A system on a chip (SoC) comprising:

• a memory controller;
• and
• a processor coupled with the memory controller, the processor comprising:
• a register to store a configuration value for tiles;
• decode circuitry to decode an instruction, the instruction having a field to identify a plurality of non-consecutive vector registers, a field to identify a register to store a base, and a field to identify a register to store an index, wherein the plurality of non-consecutive vector registers are to store 64-bit data elements, and wherein the plurality of non-consecutive vector registers are to have a single-instruction, multiple-data (SIMD) dimension based on the configuration value for the tiles;
• and
• execution circuitry coupled with the decode circuitry, the execution circuitry to perform operations corresponding to the instruction, including to store the 64-bit data elements from the plurality of non-consecutive vector registers to destination memory locations generated using the base and the index.

A non-transitory machine-readable storage medium storing instructions that, when executed by a machine, are to cause the machine to perform operations, including to:

• store a configuration value for tiles in a register;
• decode an instruction, the instruction having a field to identify a plurality of non-consecutive vector registers, a field to identify a register to store a base, and a field to identify a register to store an index, wherein the plurality of non-consecutive vector registers are to store 64-bit data elements, and wherein the plurality of non-consecutive vector registers are to have a single-instruction, multiple-data (SIMD) dimension based on the configuration value for the tiles;
• and
• perform operations corresponding to the instruction, including to store the 64-bit data elements from the plurality of non-consecutive vector registers to destination memory locations generated using the base and the index.

An apparatus comprising:

• a plurality of caches at a plurality of different cache levels;
• programmable configuration storage to store configuration information for a matrix, the configuration information to include a first value corresponding to a number of rows for the matrix, a second value corresponding to a number of columns for the matrix, and a start row value corresponding to a row of the matrix at which to restart execution of a matrix store instruction;
• a fetch circuitry to fetch the matrix store instruction;
• decode circuitry to decode the matrix store instruction, the matrix store instruction having a first operand to reference one or more memory addresses and a second operand to specify one or more registers;
• and
• execution circuitry, coupled to the programmable configuration storage and the decode circuitry, the execution circuitry to perform operations corresponding to the matrix store instruction, including to store the matrix, from the one or more registers specified by the second operand, to the one or more memory addresses referenced by the first operand.