Systems, methods, and apparatuses for tile transpose

A method comprising:

• executing, by execution circuitry of a core that is coupled to a first memory via a memory controller, first instructions of a first instruction set architecture (ISA);
• causing, by the core, one or more matrix processing instructions of a second ISA to be communicated to a matrix operations accelerator coupled to the first memory via the memory controller;
• and
• executing, by the matrix operations accelerator, the one or more matrix processing instructions of the second ISA to perform matrix operations with a source matrix tile comprising a first plurality of source data elements, the matrix operations accelerator integral to the core or coupled to the core via an interconnect, the matrix operations accelerator to:
• receive the one or more matrix processing instructions of the second ISA from the first memory, at least one instruction of the one or more matrix processing instructions having fields for an opcode to indicate a matrix transpose operation and a source matrix tile operand identifier to indicate the source matrix tile to be transposed, the source matrix tile comprising a plurality of 32-bit data elements, and
• execute the one or more matrix processing instructions to perform the matrix transpose operation on the source matrix tile to generate a result matrix tile comprising a transpose of the source matrix tile, the matrix transpose operation to transform each row of the 32-bit data elements of the source matrix tile into a corresponding column of 32-bit data elements of the result matrix tile.

A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform operations comprising:

• executing, by execution circuitry of a core that is coupled to a first memory via a memory controller, first instructions of a first instruction set architecture (ISA);
• causing, by the core, one or more matrix processing instructions of a second ISA to be communicated to a matrix operations accelerator coupled to the first memory via the memory controller;
• and
• executing, by the matrix operations accelerator, the one or more matrix processing instructions of the second ISA to perform matrix operations with a source matrix tile comprising a first plurality of source data elements, the matrix operations accelerator integral to the core or coupled to the core via an interconnect, the matrix operations accelerator to:
• receive the one or more matrix processing instructions of the second ISA from the first memory, at least one instruction of the one or more matrix processing instructions having fields for an opcode to indicate a matrix transpose operation and a source matrix tile operand identifier to indicate the source matrix tile to be transposed, the source matrix tile comprising a plurality of 32-bit data elements, and
• execute the one or more matrix processing instructions to perform the matrix transpose operation on the source matrix tile to generate a result matrix tile comprising a transpose of the source matrix tile, the matrix transpose operation to transform each row of the 32-bit data elements of the source matrix tile into a corresponding column of 32-bit data elements of the result matrix tile.