G06F 7/533
Reduction of the number of iteration steps or stages
Official title: Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
G06F7/533 (Reduction of the number of iteration steps or stages) appears on 475 US grants and 229 published applications in this corpus.
Search patents in G06F- Granted patents
- 475
- Published applications
- 229
- Assignees
- 188
- Inventors
- 770
- Latest grant
- 26 Aug 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 3 | 0 |
| 1978 | 4 | 0 |
| 1979 | 4 | 0 |
| 1980 | 7 | 0 |
| 1981 | 0 | 0 |
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 2 | 0 |
| 1985 | 3 | 0 |
| 1986 | 3 | 0 |
| 1987 | 7 | 0 |
| 1988 | 7 | 0 |
| 1989 | 18 | 0 |
| 1990 | 9 | 0 |
| 1991 | 12 | 0 |
| 1992 | 6 | 0 |
| 1993 | 14 | 0 |
| 1994 | 18 | 0 |
| 1995 | 12 | 0 |
| 1996 | 10 | 0 |
| 1997 | 13 | 0 |
| 1998 | 24 | 0 |
| 1999 | 24 | 0 |
| 2000 | 23 | 0 |
| 2001 | 23 | 5 |
| 2002 | 17 | 13 |
| 2003 | 13 | 18 |
| 2004 | 15 | 19 |
| 2005 | 10 | 10 |
| 2006 | 11 | 11 |
| 2007 | 14 | 12 |
| 2008 | 10 | 9 |
| 2009 | 13 | 12 |
| 2010 | 13 | 3 |
| 2011 | 5 | 4 |
| 2012 | 10 | 10 |
| 2013 | 5 | 16 |
| 2014 | 15 | 6 |
| 2015 | 6 | 7 |
| 2016 | 9 | 2 |
| 2017 | 7 | 3 |
| 2018 | 3 | 3 |
| 2019 | 4 | 11 |
| 2020 | 14 | 18 |
| 2021 | 9 | 7 |
| 2022 | 6 | 6 |
| 2023 | 11 | 4 |
| 2024 | 3 | 7 |
| 2025 | 4 | 11 |
| 2026 | 0 | 2 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Multiplier, multiply-accumulate circuit, and convolution operation unit26 Aug 2025US 12,399,686 B2Shenzhen Microbt Electronics Technology Co., Ltd.
- Processing element, neural processing device including same, and multiplication operation method using same25 Feb 2025US 12,236,209 B2Rebellions Inc.
- Rank-based dot product circuitry14 Jan 2025US 12,197,888 B2Altera Corporation
- Multiplier and adder in systolic array14 Jan 2025US 12,197,890 B2Google Inc.
- Low power hardware architecture for handling accumulation overflows in a convolution operation10 Dec 2024US 12,165,041 B2Recogni Inc.
- Dot product reduction tree for sign-extension encoding1 Oct 2026US 2026/0299884 A1Advanced Micro Devices, Inc.
- Electronic device performing calculation using artificial intelligence model, and method for operating electronic device14 May 2026US 2026/0133763 A1Samsung Electronics Co., Ltd.
- Shared Partial Products for a Dot Product Operation in Hardware11 Dec 2025US 2025/0378133 A1
- Multiplier-accumulator circuit with path matching20 Nov 2025US 2025/0355623 A1British Cayman Islands Intelligo Technology Inc.
- Mixed-Radix Multiplier Circuit2 Oct 2025US 2025/0306854 A1
Most cited
By later US patents
- Multiplier circuit design for a programmable logic device172US 5,754,459 AXilinx, Inc. · 1998
- Multiplying unit in a computer system, capable of population counting155US 4,989,168 AFujitsu Limited · 1991
- Reconfigurable processor devices151US 6,353,841 B1Elixent Limited · 2002
- Method and apparatus for computing a sum of packed data elements using SIMD multiply circuitry121US 6,377,970 B1Intel Corporation · 2002
- Floating point data processor for high speech operation120US 4,075,704 AFloating Point Systems, Inc. · 1978