Multiplier, multiply-accumulate circuit, and convolution operation unit

A convolution operation unit, comprising a plurality of multiply-accumulate circuits configured to run in parallel, wherein each of the plurality of multiply-accumulate circuit is configured to receive a same preset multiple of a same first operand in a same operation period, and each multiply-accumulate circuit comprises:

• a plurality of multipliers configured to run in parallel, wherein each multiplier is configured to perform a multiplication operation between the first operand and a second operand, the second operand is divided into one or more third operands by bit, and each multiplier comprises:
• one or more selection circuits, wherein each of the one or more selection circuits is respectively configured to select a target preset multiple of the first operand from the preset multiple of the first operand as a fourth operand according to a corresponding third operand, the target preset multiple is equal to a value of the third operand;
• and
• a partial product summing circuit, wherein each of one or more input terminals of the partial product summing circuit is respectively connected to an output terminal of corresponding one of the one or more selection circuits, and the partial product summing circuit is configured to calculate a partial product sum of one or more fourth operands from the one or more selection circuits;
• and
• an accumulative summing circuit, wherein an input terminal of the accumulative summing circuit is respectively connected to an output terminal of corresponding one of the plurality of multipliers, and the accumulative summing circuit is configured to calculate an accumulative sum of products between a plurality of sets of the first operands and the second operands according to a plurality of outputs from the plurality of multipliers.