Processing element, neural processing device including same, and multiplication operation method using same

A processor comprising processing circuitry comprising:

• a weight register configured to store a weight;
• an input activation register configured to store an input activation;
• first and second multiplier circuits configured to generate partial multiplication groups by performing a multiplication operation of the weight stored in the weight register and the input activation stored in the input activation register;
• a digital aligning circuit configured to generate a first aligned partial multiplication group and a second aligned partial multiplication group by aligning the partial multiplication groups with same number of digits when a calculation mode signal is first mode signal associated with a first precision wherein the first aligned partial multiplication group is calculated by using a first booth reduction tree and the second aligned partial multiplication group is calculated by using a second booth reduction tree;
• a first adder circuit configured to generate result data by using one of the first and the second aligned partial multiplication groups with the first mode signal or a second adder circuit configured to generate the result data by using one of the partial multiplication groups with a second mode signal associated with a second precision smaller than the first precision;
• and
• a third adder circuit configured to generate a partial sum by using the result data.

An operation method of a processing circuitry comprising a weight register, an input activation register, a first multiplier circuit, a second multiplier circuit, a digit aligning circuit, a first adder circuit, a second adder circuit, and a third adder circuit, the operation method comprising:

• storing, by the weight register, a weight;
• storing, by the input activation register, an input activation;
• generating, by the first and the second multiplier circuits, partial multiplication groups by performing a multiplication operation of the weight stored in the weight register and the input activation stored in the input activation register;
• generating, by the digital aligning circuit, a first aligned partial multiplication group and a second aligned partial multiplication group by aligning the partial multiplication groups with same number of digits wherein the first aligned partial multiplication group is calculated by using a first booth reduction tree and the second aligned partial multiplication group is calculated by using a second booth reduction tree;
• generating, by the first and the second adder circuits result data by using one of the partial multiplication groups or one of the first and the second aligned partial multiplication groups;
• and
• generating, by the third adder circuit, a partial sum by using the result data.