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US 12,197,888 B2Granted
Rank-based dot product circuitry
AssigneeAltera Corporation
InventorMartin Langhammer
Life of this patent
Estimating the term…
Abstract
Integrated circuits with dot product circuitry are provided. The dot product circuitry may be configured to generate partial products of different ranks based on the inputs. The partial products may be organized into corresponding groups based on their ranks. Each group of partial products having the same rank can then be compressed using a compressor/reduction tree. At least some of the compressed partial product values may be shifted between the different groups to maintain the proper offset. Each partial product may have an associated one's to two's complement conversion bit. The conversion bits of the various partial product groups can be separately aggregated and then injected into the compressor tree at one or more locations.
Claims20
An integrated circuit, comprising:
- a partial product generation circuit configured to;
- receive input operands and generate partial products grouped into a first group of the partial products all having a first rank and a second group of the partial products all having a second rank that is different than the first rank, wherein the second rank is shifted relative to the first rank;
- a first compressor circuit configured to compress the first group of the partial products into first vectors;
- and
- a second compressor circuit configured to compress the second group of the partial products into second vectors;
- first shifting circuits configured to shift the second vectors relative to the first vectors and output second shifted vectors;
- a third compressor circuit configured to receive a third group of partial products all having a third rank that is different from the first rank or the second rank and configured to output third vectors;
- a fourth compressor circuit configured to receive a fourth group of partial products all having a fourth rank that is different from the first rank, the second rank, or the third rank and configured to output fourth vectors;
- second shifting circuits configured to shift the fourth vectors relative to the third vectors to generate fourth shifted vectors;
- a fifth compressor circuit configured to compress the first vectors and the second shifted vectors and configured to output fifth vectors;
- a sixth compressor circuit configured to compress the third vectors and the fourth shifted vectors and configured to output sixth vectors;
- third shifting circuits configured to shift the sixth vectors relative to the fifth vectors;
- and
- a multiplexer configured to selectively bypass the third shifting circuits to support a plurality of input precisions based on a multiplexer.
11 more elements
An integrated circuit, comprising:
- partial product generation circuitry configured to receive input signals and to generate a plurality of partial products grouped into a first group of the partial products all having a first rank and a second group of the partial products all having a second rank that is different than the first rank, wherein the second rank is shifted relative to the first rank;
- and
- a compressor tree divided into a plurality of compressor groups organized based on a rank of respective groups of the plurality of partial products received at respective compressor groups of the plurality of compressor groups, wherein the respective compressor groups are configurable to:
- compress the first group of the partial products into first vectors;
- and
- compress the second group of the partial products into second vectors;
- and
- a multiplexer configurable to select only a first one's to two's complement conversion bit aggregation circuit during a first precision mode and select only a second one's to two's complement conversion bit aggregation circuit during a second precision mode.
5 more elements
An integrated circuit, comprising:
- dot product circuitry decomposed into:
- a first dot group comprising a first number of multiplies having a first rank;
- a second dot group comprising a second number of multiplies having a second rank that is shifted relative to the first rank by a number of conversion bits;
- a first aggregation circuit configured to aggregate first conversion bits associated with the first dot group;
- a second aggregation circuit configured to aggregate second conversion bits associated with the second dot group;
- a compressor configured to compress the first conversion bits received from the first aggregation circuit and the second conversion bits received from the second aggregation circuit;
- a plurality of one's to two's complement conversion bit aggregation circuit configured to generate at least one vector that is injected at a single point in the compressor;
- and
- a multiplexer configured to select only a first one's to two's complement conversion bit aggregation circuit of the plurality of one's to two's complement conversion bit aggregation circuit during a first precision mode and to select only a second one's to two's complement conversion bit aggregation circuit of the plurality of one's to two's complement conversion bit aggregation circuit during a second precision mode.
6 more elements
Dependencies are inferred from the claim text.