G06F 7/4912
Adding
Official title: {Adding; Subtracting (G06F7/492, G06F7/498 take precedence)}
G06F7/4912 (Adding) appears on 21 US grants and 21 published applications in this corpus.
Search patents in G06F- Granted patents
- 21
- Published applications
- 21
- Assignees
- 15
- Inventors
- 41
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 2 | 0 |
| 1999 | 1 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 0 |
| 2003 | 1 | 0 |
| 2004 | 0 | 0 |
| 2005 | 0 | 0 |
| 2006 | 0 | 2 |
| 2007 | 0 | 1 |
| 2008 | 0 | 1 |
| 2009 | 2 | 3 |
| 2010 | 1 | 1 |
| 2011 | 0 | 0 |
| 2012 | 2 | 0 |
| 2013 | 3 | 0 |
| 2014 | 0 | 2 |
| 2015 | 1 | 0 |
| 2016 | 0 | 0 |
| 2017 | 0 | 0 |
| 2018 | 1 | 1 |
| 2019 | 1 | 1 |
| 2020 | 0 | 1 |
| 2021 | 1 | 3 |
| 2022 | 0 | 0 |
| 2023 | 2 | 3 |
| 2024 | 1 | 0 |
| 2025 | 0 | 1 |
| 2026 | 1 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Sign-efficient addition and subtraction for streaming computations in cryptographic engines29 Sep 2026US 12,750,217 B2Cryptography Research, Inc.
- In-memory bit-serial addition system15 Oct 2024US 12,118,328 B2Purdue Research Foundation
- Differential privacy security for benchmarking26 Dec 2023US 11,853,461 B2Workday, Inc.
- In-memory bit-serial addition system6 Jun 2023US 11,669,302 B2Purdue Research Foundation
- Differential privacy security for benchmarking6 Apr 2021US 10,970,417 B1Workday, Inc.
- Programming of parameters for nonlinear function in neural processor5 Mar 2026US 2026/0064364 A1Apple Inc.
- Optimized multiply-accumulate operator for ai calculations30 Jan 2025US 2025/0036362 A1
- In-memory bit-serial addition system28 Sep 2023US 2023/0305804 A1Purdue Research Foundation
- Data processing method implemented at edge switch, electronic device, and program product27 Jul 2023US 2023/0236795 A1Dell Products L. P.
- Sign-efficient addition and subtraction for streamingcomputations in cryptographic engines9 Feb 2023US 2023/0042366 A1Cryptography Research, Inc.
Most cited
By later US patents
- Decimal arithmetic apparatus and method8US 5,745,399 AInternational Computers Limited · 1998
- High-speed radix 100 parallel adder8US 6,546,411 B1International Business Machines Corporation · 2003
- System and method for performing decimal floating point addition8US 7,519,645 B2International Business Machines Corporation · 2009
- Combined binary/decimal adder unit7US 5,928,319 AInternational Business Machines Corporation · 1999
- Method for performing decimal floating point addition4US 8,161,091 B2International Business Machines Corporation · 2012