Combined binary/decimal adder unit

A combined binary/decimal adder unit (10) comprising a sum logic for generating a binary rough sum of each decimal digit of a plurality of operands, a digit carry logic (34) for generating binary carries within the decimal digits and carries out of the decimal digits, and a correction logic performing a six correction of decimal sum digits which are in the invalid range, the adder unit characterized by:

• (a) a first correction logic (26) for adding a plus six correction value to each decimal digit of a first one of the operands;
• (b) a second correction logic (24) for adding a minus six correction value to each decimal digit of a second one of the operands;
• (c) a pre-sum logic (36, 38) for receiving the output of the first correction logic and receiving said first one of said operands in an uncorrected state and for receiving the output of the second correction logic and receiving the second one of said operands in an uncorrected state and for generating in each position of the decimal digits a first set of sums of the corrected and uncorrected operands under the presumption of a zero carry input into the decimal digit position and a second set of sums of corrected and uncorrected operands under the presumption of a one carry input into the decimal digit position;
• and
• (d) a selection logic (M5-M8) operating in response to a digit carry-in signal (INIT.sub.13 CARRY.sub.13 in, DCy59), to carry-out signals from the digit carry logic (34) and to an operation control signal (DEC.sub.13 ADD, DEC.sub.13 SUB) for selecting one of the pre-sums from the first or second set of sums as the correct sum of the decimal digit position.