High-speed radix 100 parallel adder

A radix 100 parallel adder comprising:

• a first logic level for receiving at least two operands, each operand including at least one radix 100 digit having seven bit positions partitioned into a low-order group and a high-order group, and for generating outputs comprising a bit carry propagate value, a bit carry generate value, and half sum value for each bit position;
• a second logic level for receiving the output from the first logic level and for generating outputs comprising group carry propagate values and group carry generate values wherein the second logic level generates a low-order group carry generate value, a low-order group carry propagate value, a high-order group carry generate (K) value, and a high-order group carry propagate (L) value;
• a third logic level for receiving the output from the second logic level and for generating outputs comprising a digit carry-out value;
• a fourth logic level for receiving the outputs from first logic level and for generating outputs comprising bit carry values;
• a fifth logic level for receiving the output from the second logic level and for generating outputs comprising a digit group carry generate and a digit group carry propagate for the at least one radix 100 digit;
• and
• a sixth logic level for receiving the output from the first logic level and the outputs from the fourth logic level and for generating a final sum for the at least one radix 100 digit.