Sign-efficient addition and subtraction for streaming computations in cryptographic engines

A cryptographic processor to perform a modular addition of a first number and a second number, the cryptographic processor comprising:

• a first multiplication circuit configured to:
• perform a multiplication operation to obtain the first number comprising a first plurality of multiple-bit words;
• an addition circuit configured to receive from the first multiplication circuit, the first plurality of multiple-bit words of the first number in an order starting from a least significant word (LSW) of the first number, wherein a sign of the first number is determined by a most significant word (MSW) of the first number;
• obtain the second number comprising a second plurality of multiple-bit words of the second number in the order starting from an LSW of the second number, wherein a sign of the second number is determined by an MSW of the second number;
• and
• compute a sum of the first number and the second number;
• a second multiplication circuit to compute a first multiplication product of (i) the sum of the first number and the second number and (ii) a number that is based on an inverse, modulo a radix number, modulus of the modular addition, the radix number being a power of two, 2n, with n not exceeding 6;
• and
• a bit-shifting circuit to bit-shift, by n bits, the sum of the first number and the second number modified using the first multiplication product to obtain an output of the modular addition, wherein the number that is based on the inverse on the modulus of the modular addition is selected to determine an LSW of the output of the modular addition based on the LSW of the first number and the LSW of the second number before a sign of the output of the modular addition is determined.

A method to perform a modular addition of a first number and a second number, the method comprising:

• computing, by an addition circuit, a sum of the first number and the second number;
• computing, by a multiplication circuit, a first multiplication product of (i) the sum of the first number and the second number and (ii) a number that is based on an inverse, modulo a radix number, modulus of the modular addition, the radix number being a power of two, 2n, with n not exceeding 6;
• and
• bit-shifting by n bits, using a bit-shifting circuit, the sum of the first number and the second number modified using the first multiplication product to obtain an output of the modular addition.