G06F 2212/683
Invalidation
G06F2212/683 (Invalidation) appears on 374 US grants and 378 published applications in this corpus.
Search patents in G06F- Granted patents
- 374
- Published applications
- 378
- Assignees
- 52
- Inventors
- 713
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1987 | 2 | 0 |
| 1988 | 1 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 1 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 0 | 0 |
| 2000 | 1 | 0 |
| 2001 | 1 | 0 |
| 2002 | 0 | 3 |
| 2003 | 3 | 0 |
| 2004 | 2 | 2 |
| 2005 | 1 | 2 |
| 2006 | 0 | 6 |
| 2007 | 5 | 8 |
| 2008 | 5 | 7 |
| 2009 | 8 | 6 |
| 2010 | 6 | 4 |
| 2011 | 4 | 6 |
| 2012 | 8 | 4 |
| 2013 | 8 | 19 |
| 2014 | 5 | 17 |
| 2015 | 24 | 16 |
| 2016 | 26 | 34 |
| 2017 | 36 | 34 |
| 2018 | 32 | 32 |
| 2019 | 34 | 37 |
| 2020 | 38 | 41 |
| 2021 | 29 | 16 |
| 2022 | 22 | 23 |
| 2023 | 22 | 20 |
| 2024 | 23 | 18 |
| 2025 | 18 | 16 |
| 2026 | 9 | 7 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Shared translation page tables for ownership transfer8 Sep 2026US 12,730,660 B1Amazon Technologies, Inc.
- Coordinated allocation of external memory16 Jun 2026US 12,656,966 B2Kove IP, LLC
- Apparatus and method for efficient management of multi-level memory2 Jun 2026US 12,645,593 B2Intel Corporation
- Address translation prefetching for input/output devices2 Jun 2026US 12,645,604 B2Microsoft Technology Licensing, LLC
- Protection against translation lookup request flooding7 Apr 2026US 12,596,654 B2Intel Corporation
- Optimizing smmu cache invalidation27 Aug 2026US 2026/0252493 A1QUALCOMM Incorporated
- Techniques for performing hardware address sanitization for memory using address tagging27 Aug 2026US 2026/0252495 A1QUALCOMM Incorporated
- Broadcast translation lookaside buffer invalidation2 Jul 2026US 2026/0186784 A1
- Technologies for preventing fault exception probing7 May 2026US 2026/0127065 A1SiFive, Inc.
- Efficient Address Translation Cache Invalidation in Data Storage Devices30 Apr 2026US 2026/0119409 A1SanDisk Technologies LLC
Most cited
By later US patents
- Apparatus and method for TLB purge reduction in a multi-level machine system246US 5,317,705 AInternational Business Machines Corporation · 1994
- Data reduction techniques in a flash-based key/value cluster storage200US 9,606,870 B1EMC IP Holding Company LLC · 2017
- Providing global translations with address space numbers121US 6,604,187 B1Advanced Micro Devices, Inc. · 2003
- Virtual memory address translation mechanism with combined hash address table and inverted page table113US 4,680,700 AInternational Business Machines Corporation · 1987
- Virtual memory address translation mechanism with controlled data persistence88US 4,638,426 AInternational Business Machines Corporation · 1987