Virtual memory address translation mechanism with controlled data persistence

In a data processing system, including a CPU and a large hierarchical memory a method for translating virtual memory addresses into real memory address which comprises:

• the CPU generating a first virtual address comprising a segment identifier portion, a page offset portion and a byte offset portion (within the page),
• using the sement identifier to access one of a plurality of segment registers pointed to by the segment identifier, each of which contains a second virtual address pointing to a large virtual block of data,
• combining said second virtual address with the page offset and byte offset portions of said first virtual address to form a third virtual address wherein said third virtual address is substantially larger than said first virtual address,
• utilizing said second virtual address and said page offset portion of said first virtual address as a virtual page search argument in a translation look-aside buffer (TLB) which comprises a very high speed searching mechanism for searching for a limited number of virtual addresses and for accessing real addresses stored therein which are translations of each related virtual address,
• accessing said TLBs utilizing a subset of the search argument as an address,
• comparing the virtual page search argument with the contents of a selected field of the accessed TLB,
• upon a successful comparison, utilizing a real page address stored therein as the translation of said virtual address and,
• accessing additional fields at the accessed location in said TLB for accessing and data persistence control information relevant to the data stored at the translated real page address,
• and if unsuccessful initiating a search in the page frame tables in main memory,
• which contain the real address corresponding to all virtual addresses utilized in the memory system at any point in time,
• generating an address in the page frame tables as a function of the virtual page search argument,
• accessing said page frame table at said generated address which address identifies the initial member of a linked list list of entries and comparing said virtual page search argument with a virtual page identifier stored at each entry storage location in said page frame tables until a successful comparison occurs.

In a high speed electronic data processing system including a central processing unit (CPU) and a large hierarchical memory system provided with a virtual addressing space significantly larger than the actual memory, the improvement which comprises an address translation mechanism for converting virtual addresses into real memory addresses including,

• means for generating a first virtual address which comprises a segment identifier field, a page offset field and a byte offset field,
• a plurality of segment registers and means for loading same under program control with a second virtual address identifying a large virtual block of data,
• means for accesssing one of said segments registers specified by said segment identifier field of said first virtual address,
• means for concatenating the virtual address from the specified segment register with the page offset and byte offset fields of said first virtual address to form a large virtual effective address comprising an effective page address portion and a byte offset portion,
• a high speed translation look-aside buffer system for storing address translation data for most recently used virtual accesses to the memory hierarchy,
• means for utilizing at least a portion of said effective page address to access the translation look-aside buffer system to determine is said effective page address has been previously translated and, if so,
• means for accessing the real page address from the translation look-aside buffer as the result of the translation process.

A high speed translation look-aside buffer (TLB) mechanism for use with a virtual to real address translation system comprising

• as many addressable storage locations therein as there are virtual to real address translation data entities, means in each storage location for storing;
• a virtual address tag for comparison with a virtual address to be translated,
• the real address in memory of the data referenced by the above virtual address, access control and identifier data relating to the data, stored at said real address in memory,
• a series of "N" lock bits for use in insuring data persistence for a particular memory page wherein "N" is the number of lines in the page, p1 means for accessing said "N" lock bits stored in said translation look-aside buffers, said plurality of lock bits comprising a bit for each line within an associated real page and means for setting said lock bits to control copy back and journalling operations when the current version of data stored in memory is accessed by the CPU and
• means operable under program control for accessing or altering data stored in storage location in said TLB based on a subset of the virtual address to be translated.