Apparatus and method for TLB purge reduction in a multi-level machine system

A computer system having a real processor and a random access memory, the computer system having a host hypervisor operating with virtual machines, and guests operating in any address translation mode of:

• a virtual=fixed guest, a virtual=real guest and a pageable guest, the system comprising
• translation lookaside buffer means in the processor for storing guest-translated virtual addresses and associated absolute addresses provided for virtual machines executing at plural guest address translation levels,
• a region relocation facility (RRF) mode indicator which is set on when the memory is divided into fixed contiguous memory locations for use by different virtual=fixed guests,
• a pageable-guest-was-processed (PGWP) indicator associated with the buffer means, the PGWP indicator being set on when a pageable guest's address translation information is stored in any entry in the buffer means, and the PGWP indicator being set of when the buffer means is purged by invalidation of all entries in the buffer means,
• means for signalling to the buffer means an invalidation request provided by a program, the request containing a table index for locating entry(s) in the buffer means to be invalidated and indicating a particular translation level for the request,
• means responsive to the signalling means for invalidating all entries in the buffer means upon detecting predetermined combined settings of the PGWP indicator and the region relocation facility mode indicator, and the signalling means indicating a translation level other than a lowest guest translation level.