Apparatus and method for efficient management of multi-level memory

A computing system, comprising:

• a multi-level main memory comprising volatile near memory and far memory comprising volatile or non-volatile memory;
• a processor, external to the multi-level main memory and including,
• a plurality of processing cores;
• and
• an integrated memory controller coupled to the multi-level main memory, the memory controller to maintain first and second caches, the first cache to cache pages recently accessed from the far memory, the second cache to cache addresses of pages recently accessed from the far memory, the memory controller to look into the first cache for pages that are mapped to the far memory before looking to the far memory for the pages that are mapped to the far memory, the second cache having a first level and a second level, the first level to cache addresses of pages that are more recently accessed than pages whose respective addresses are cached in the second level, the memory controller to inform system software of either or both of a) and b) below:
• a) that a first page in the first cache that is accessed less than other pages in the first cache is a candidate for migration from the far memory to the near memory;
• b) that a second page whose address travels a threshold number of round trips between the first and second levels of the second cache is a candidate for migration from the far memory to the near memory.

A non-transitory machine readable storage medium containing program code that when processed by a computer causes the computer to perform a method, comprising:

• receiving an indication from a memory controller integrated on a chip that interfaces with a multi-level memory comprising volatile near memory external to the chip and far memory comprising volatile or non-volatile memory external to the chip, the memory controller to maintain first and second caches, the first cache to cache pages recently accessed from the far memory, the memory controller to look into the first cache for pages that are mapped to the far memory before looking to the far memory for the pages that are mapped to the far memory, the second cache to cache addresses of pages recently accessed from the far memory, the second cache having a first level and a second level, the first level to cache addresses of pages that are more recently accessed than pages whose respective addresses are cached in the second level, the indication being any of a) and b) below:
• a) that a first page in the first cache that is accessed less than other pages in the first cache is a candidate for migration from the far memory to the near memory;
• b) that a second page whose address travels a threshold number of round trips between the first and second levels of the second cache is a candidate for migration from the far memory to the near memory.