G06F 2212/50
Control mechanisms for virtual memory, cache or tlb
Official title: Control mechanisms for virtual memory, cache or TLB
G06F2212/50 (Control mechanisms for virtual memory, cache or tlb) appears on 1,691 US grants and 1,861 published applications in this corpus.
Search patents in G06F- Granted patents
- 1,691
- Published applications
- 1,861
- Assignees
- 309
- Inventors
- 3,522
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1984 | 2 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 1 | 0 |
| 1992 | 1 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 2 | 0 |
| 1996 | 3 | 0 |
| 1997 | 3 | 0 |
| 1998 | 2 | 0 |
| 1999 | 3 | 0 |
| 2000 | 5 | 0 |
| 2001 | 2 | 1 |
| 2002 | 9 | 11 |
| 2003 | 5 | 9 |
| 2004 | 7 | 29 |
| 2005 | 5 | 18 |
| 2006 | 17 | 18 |
| 2007 | 12 | 21 |
| 2008 | 29 | 24 |
| 2009 | 14 | 33 |
| 2010 | 20 | 18 |
| 2011 | 22 | 19 |
| 2012 | 25 | 25 |
| 2013 | 37 | 40 |
| 2014 | 37 | 49 |
| 2015 | 59 | 71 |
| 2016 | 78 | 94 |
| 2017 | 80 | 89 |
| 2018 | 89 | 121 |
| 2019 | 116 | 153 |
| 2020 | 171 | 179 |
| 2021 | 165 | 131 |
| 2022 | 133 | 167 |
| 2023 | 150 | 158 |
| 2024 | 159 | 174 |
| 2025 | 150 | 118 |
| 2026 | 78 | 91 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- System and method for facilitating dynamic command management in a network interface controller (NIC)6 Oct 2026US 12,754,857 B2Hewlett Packard Enterprise Development LP
- Backward compatibility testing of software in a mode that attempts to induce skew15 Sep 2026US 12,737,282 B2Sony Interactive Entertainment Inc.
- System and method of inter/intra-memory tiering25 Aug 2026US 12,717,485 B2Samsung Electronics Co., Ltd.
- Accelerating storage I/O operations using cached data querying25 Aug 2026US 12,717,713 B2Everpure, Inc.
- Integrated circuit chip to selectively provide tag array functionality or cache array functionality25 Aug 2026US 12,717,717 B2Intel Corporation
- Elastic configuration of data rate control parameters in a memory sub-system with single-level cell memory caching27 Aug 2026US 2026/0252489 A1Micron Technology, Inc.
- Prefetcher with Multi-Cache Level Prefetches and Feedback Architecture27 Aug 2026US 2026/0252490 A1SiFive, Inc.
- Interface circuitry13 Aug 2026US 2026/0236385 A1Arm Limited
- Timed data transfer between a host system and a memory sub-system13 Aug 2026US 2026/0236399 A1Micron Technology, Inc.
- Shared Cache Management Method and Electronic Device30 Jul 2026US 2026/0219969 A1Honor Device Co., Ltd.
Most cited
By later US patents
- Parallel compression/decompression system and method for implementation of in-memory compressed cache improving storage density and access speed for industry standard memory subsystems and in-line memory modules366US 6,523,102 B1Interactive Silicon, Inc. · 2003
- System and method for dynamically controlling cache management291US 5,381,539 AEMC Corporation · 1995
- Efficient live-mount of a backed up virtual machine in a storage management system249US 9,436,555 B2Commvault Systems, Inc. · 2016
- Logical sector mapping in a flash storage array246US 9,454,477 B2Pure Storage, Inc. · 2016
- Logical sector mapping in a flash storage array244US 9,454,476 B2Pure Storage, Inc. · 2016