US 12,717,717 B2 · Integrated circuit chip to selectively provide tag array functionality or cache array functionality

Abstract

Techniques and mechanisms for selectively configuring an integrated circuit (IC) chip to provide tag array functionality and/or cache array functionality. In an embodiment, an IC chip comprises a first array of memory cells, a second array of memory cells, and a cache controller. Based on whether the IC chip is coupled to another IC chip, selector circuitry of the IC chip configures one of multiple possible modes of the cache controller. A first mode of the multiple modes is to provide tag array functionality with the first array, and cache array functionality with the second memory cell array. A second mode of the multiple modes is to provide tag array functionality with the second memory cell array, and cache array functionality with a remote array of memory cells. In another embodiment, the cache controller is reconfigured to another mode based on a change to a power consumption characteristic.

Claims20

Dependent claims

An apparatus comprising:

a first memory cell array and a second memory cell array;
a cache controller;
detector circuitry to detect a connectivity condition of the apparatus, comprising the detector circuitry to determine whether the apparatus is coupled to an external device which comprises a third memory cell array that is to provide a cache array functionality;
selector circuitry to perform a selection, based on the connectivity condition, which selects one mode from among multiple modes of the cache controller, wherein the multiple modes comprise:
a first mode which is to provide a tag array functionality with the first memory cell array, and which is further to provide the cache array functionality with the second memory cell array;
and
a second mode which is to provide the tag array functionality with the second memory cell array;
wherein, based on the selection, the selector circuitry is to signal the cache controller to transition to the one mode.

5 more elements

A non-transitory computer-readable storage media which, when executed by a processor, causes the processor to perform a method comprising:

detecting a connectivity condition of an apparatus which comprises a first memory cell array and a second memory cell array, comprising determining whether the apparatus is coupled to an external device which comprises a third memory cell array that is to provide a cache array functionality;
based on the connectivity condition, performing a selection of one mode from among multiple modes of a cache controller of the apparatus, wherein the multiple modes comprise:
a first mode which is to provide a tag array functionality with the first memory cell array, and which is further to provide the cache array functionality with the second memory cell array;
and
a second mode which is to provide the tag array functionality with the second memory cell array, and which is further to provide the cache array functionality with the third memory cell array;
based on the selection, transitioning the cache controller to the one mode;
and
based on the one mode, operating one of the first memory cell array or the second memory cell array as a tag array.

5 more elements

Dependencies are inferred from the claim text.

Integrated circuit chip to selectively provide tag array functionality or cache array functionality

Life of this patent

Integrated circuit chip to selectively provide tag array functionality or cache array functionality

Life of this patent

Abstract

Claims20