Shared Cache Management Method and Electronic Device
AssigneeHonor Device Co., Ltd.
InventorsZhenguo Mu, Shichu Zhang, Jun Xiao
Life of this patent
Estimating the term…
Abstract
A shared cache management method may match a processor and a running frequency of a shared cache, so that the processor can obtain data from the shared cache in a timely manner, thereby improving a running speed of an application. The method includes: setting, in response to a first event, the running frequency of the shared cache to a first frequency based on a focus application, user operation information, performance information of each processing core, and thread running information. The focus application is an application last operated by a user, the user operation information includes types and a quantity of operations performed by a user on the focus application in preset time.
Claims20
A shared cache management method applied to an electronic device comprising a processor that comprises a shared cache and N processing cores, wherein N is a positive integer, and wherein the method comprises:
- receiving a first event to trigger a focus application to change;
- and
- setting, in response to the first event, a running frequency of the shared cache to a first frequency based on the focus application, user operation information, performance information of each processing core, and thread running information,
- wherein the focus application is an application last operated by a user,
- wherein the user operation information comprises types and a quantity of operations performed by the user on the focus application in preset time,
- wherein the performance information of each processing core reflects a shared cache miss rate of the processing core,
- wherein the thread running information reflects running time proportions of a plurality of thread groups on each of the N processing cores, and
- wherein each thread group comprises one or more threads running on the electronic device.
An electronic device, comprising:
- a first processor comprising a shared cache and N processing cores, wherein N is a positive integer;
- and
- a memory coupled to the processor and storing a computer program comprising instructions that when executed by the processor, configure the electronic device to implement operations comprising:
- receiving a first event to trigger a focus application to change;
- and
- setting, in response to the first event, a running frequency of the shared cache to a first frequency based on the focus application, user operation information, performance information of each processing core, and thread running information,
- wherein the focus application is an application last operated by a user,
- wherein the user operation information comprises types and a quantity of operations performed by the user on the focus application in preset time,
- wherein the performance information of each processing core reflects a shared cache miss rate of the processing core,
- wherein the thread running information reflects running time proportions of a plurality of thread groups on each of the N processing cores, and
- wherein each thread group comprises one or more threads running on the electronic device.
A computer-readable storage medium storing a computer program configured to be executed by an electronic device comprising a processor that comprises a shared cache and N processing cores, wherein N is a positive integer, and wherein when the computer program is executed by the electronic device, the electronic device becomes configured to implement operations comprising:
- receiving a first event to trigger a focus application to change;
- and
- setting, in response to the first event, a running frequency of the shared cache to a first frequency based on the focus application, user operation information, performance information of each processing core, and thread running information,
- wherein the focus application is an application last operated by a user,
- wherein the user operation information comprises types and a quantity of operations performed by the user on the focus application in preset time,
- wherein the performance information of each processing core is used to reflect a shared cache miss rate of the processing core,
- wherein the thread running information is used to reflect running time proportions of a plurality of thread groups on each of the N processing cores, and
- wherein each thread group comprises one or more threads running on the electronic device.
Dependencies are inferred from the claim text.