Interface circuitry
AssigneeArm Limited
InventorsSven Ola Johannes HUGOSSON, Klas Magnus BRUCE
Life of this patent
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Abstract
An apparatus comprises interface circuitry to exchange signals with one or more requesters. A to-be-translated memory access request specifies a target address to be translated to identify a location in a memory system to be accessed. In response to a to-be-translated memory access request received at the interface circuitry from a given requester, the interface circuitry issues a request acknowledgement to the given requester acknowledging the to-be-translated memory access request independent of whether the to-be-translated memory access request satisfies an observability condition.
Claims20
An apparatus comprising:
- interface circuitry configured to exchange signals with one or more requesters;
- and
- control circuitry;
- wherein
- in response to a to-be-translated memory access request received at the interface circuitry from a given requester, the to-be-translated memory access request specifying a target address to be translated to identify a location in a memory system to be accessed in response to the to-be-translated memory access request, the control circuitry is configured to control the interface circuitry to issue a request acknowledgement to the given requester acknowledging the to-be-translated memory access request independent of whether the to-be-translated memory access request satisfies an observability condition.
A method comprising:
- exchanging signals with one or more requesters;
- and
- in response to a to-be-translated memory access request received from a given requester, the to-be-translated memory access request specifying a target address to be translated to identify a location in a memory system to be accessed in response to the to-be-translated memory access request, issuing a request acknowledgement to the given requester acknowledging the to-be-translated memory access request independent of whether the to-be-translated memory access request satisfies an observability condition.
A non-transitory computer-readable medium storing a computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program comprising:
- interface program logic to exchange signals with one or more requesters;
- and
- control program logic;
- wherein
- in response to a to-be-translated memory access request received by the interface program logic from a given requester, the to-be-translated memory access request specifying a target address to be translated to identify a location in a memory system to be accessed in response to the to-be-translated memory access request, the control program logic is configured to control the interface program logic to issue a request acknowledgement to the given requester acknowledging the to-be-translated memory access request independent of whether the to-be-translated memory access request satisfies an observability condition.
Dependencies are inferred from the claim text.